(match_operand:QI 2 "general_operand" "dI")))]  ""  "lsl%.b %2,%0")(define_insn "lshrsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")		     (match_operand:SI 2 "general_operand" "dI")))]  ""  "lsr%.l %2,%0")(define_insn "lshrhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")		     (match_operand:HI 2 "general_operand" "dI")))]  ""  "lsr%.w %2,%0")(define_insn "lshrqi3"  [(set (match_operand:QI 0 "general_operand" "=d")	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")		     (match_operand:QI 2 "general_operand" "dI")))]  ""  "lsr%.b %2,%0");; rotate instructions(define_insn "rotlsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(rotate:SI (match_operand:SI 1 "general_operand" "0")		   (match_operand:SI 2 "general_operand" "dI")))]  ""  "rol%.l %2,%0")(define_insn "rotlhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(rotate:HI (match_operand:HI 1 "general_operand" "0")		   (match_operand:HI 2 "general_operand" "dI")))]  ""  "rol%.w %2,%0")(define_insn "rotlqi3"  [(set (match_operand:QI 0 "general_operand" "=d")	(rotate:QI (match_operand:QI 1 "general_operand" "0")		   (match_operand:QI 2 "general_operand" "dI")))]  ""  "rol%.b %2,%0")(define_insn "rotrsi3"  [(set (match_operand:SI 0 "general_operand" "=d")	(rotatert:SI (match_operand:SI 1 "general_operand" "0")		     (match_operand:SI 2 "general_operand" "dI")))]  ""  "ror%.l %2,%0")(define_insn "rotrhi3"  [(set (match_operand:HI 0 "general_operand" "=d")	(rotatert:HI (match_operand:HI 1 "general_operand" "0")		     (match_operand:HI 2 "general_operand" "dI")))]  ""  "ror%.w %2,%0")(define_insn "rotrqi3"  [(set (match_operand:QI 0 "general_operand" "=d")	(rotatert:QI (match_operand:QI 1 "general_operand" "0")		     (match_operand:QI 2 "general_operand" "dI")))]  ""  "ror%.b %2,%0");; Special cases of bit-field insns which we should;; recognize in preference to the general case.;; These handle aligned 8-bit and 16-bit fields,;; which can usually be done with move instructions.(define_insn ""  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")			 (match_operand:SI 1 "immediate_operand" "i")			 (match_operand:SI 2 "immediate_operand" "i"))	(match_operand:SI 3 "general_operand" "d"))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[1]) == CONST_INT   && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)   && GET_CODE (operands[2]) == CONST_INT   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0   && (GET_CODE (operands[0]) == REG       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"  "*{  if (REG_P (operands[0]))    {      if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)        return \"bfins %3,[%c2,%c1]%0\";    }  else    operands[0]      = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);  if (GET_CODE (operands[3]) == MEM)    operands[3] = adj_offsettable_operand (operands[3],					   (32 - INTVAL (operands[1])) / 8);  if (INTVAL (operands[1]) == 8)    return \"mov%.b %3,%0\";  return \"mov%.w %3,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=&d")	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")			 (match_operand:SI 2 "immediate_operand" "i")			 (match_operand:SI 3 "immediate_operand" "i")))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[2]) == CONST_INT   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)   && GET_CODE (operands[3]) == CONST_INT   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0   && (GET_CODE (operands[1]) == REG       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"  "*{  if (REG_P (operands[1]))    {      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)	return \"bfextu [%c3,%c2]%1,%0\";    }  else    operands[1]      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);  output_asm_insn (\"clrl %0\", operands);  if (GET_CODE (operands[0]) == MEM)    operands[0] = adj_offsettable_operand (operands[0],					   (32 - INTVAL (operands[1])) / 8);  if (INTVAL (operands[2]) == 8)    return \"mov%.b %1,%0\";  return \"mov%.w %1,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=d")	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")			 (match_operand:SI 2 "immediate_operand" "i")			 (match_operand:SI 3 "immediate_operand" "i")))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[2]) == CONST_INT   && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)   && GET_CODE (operands[3]) == CONST_INT   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0   && (GET_CODE (operands[1]) == REG       || ! mode_dependent_address_p (XEXP (operands[1], 0)))"  "*{  if (REG_P (operands[1]))    {      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)	return \"bfexts [%c3,%c2]%1,%0\";    }  else    operands[1]      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);  if (INTVAL (operands[2]) == 8)    return \"mov%.b %1,%0\;extb%.l %0\";  return \"mov%.w %1,%0\;ext%.l %0\";}");; Bit field instructions, general cases.;; "o,d" constraint causes a nonoffsettable memref to match the "o";; so that its address is reloaded.(define_insn "extv"  [(set (match_operand:SI 0 "general_operand" "=d,d")	(sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")			 (match_operand:SI 2 "general_operand" "di,di")			 (match_operand:SI 3 "general_operand" "di,di")))]  "TARGET_68020 && TARGET_BITFIELD"  "bfexts [%c3,%c2]%1,%0")(define_insn "extzv"  [(set (match_operand:SI 0 "general_operand" "=d,d")	(zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")			 (match_operand:SI 2 "general_operand" "di,di")			 (match_operand:SI 3 "general_operand" "di,di")))]  "TARGET_68020 && TARGET_BITFIELD"  "bfextu [%c3,%c2]%1,%0")(define_insn ""  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")			 (match_operand:SI 1 "general_operand" "di,di")			 (match_operand:SI 2 "general_operand" "di,di"))        (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))		(match_operand 3 "immediate_operand" "i,i")))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[3]) == CONST_INT   && (INTVAL (operands[3]) == -1       || (GET_CODE (operands[1]) == CONST_INT           && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"  "*{  CC_STATUS_INIT;  return \"bfchg [%c2,%c1]%0\";}")(define_insn ""  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")			 (match_operand:SI 1 "general_operand" "di,di")			 (match_operand:SI 2 "general_operand" "di,di"))	(const_int 0))]  "TARGET_68020 && TARGET_BITFIELD"  "*{  CC_STATUS_INIT;  return \"bfclr [%c2,%c1]%0\";}")(define_insn ""  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")			 (match_operand:SI 1 "general_operand" "di,di")			 (match_operand:SI 2 "general_operand" "di,di"))	(const_int -1))]  "TARGET_68020 && TARGET_BITFIELD"  "*{  CC_STATUS_INIT;  return \"bfset [%c2,%c1]%0\";}")(define_insn "insv"  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")			 (match_operand:SI 1 "general_operand" "di,di")			 (match_operand:SI 2 "general_operand" "di,di"))	(match_operand:SI 3 "general_operand" "d,d"))]  "TARGET_68020 && TARGET_BITFIELD"  "bfins %3,[%c2,%c1]%0");; Now recognize bit field insns that operate on registers;; (or at least were intended to do so).(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=d")	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")			 (match_operand:SI 2 "general_operand" "di")			 (match_operand:SI 3 "general_operand" "di")))]  "TARGET_68020 && TARGET_BITFIELD"  "bfexts [%c3,%c2]%1,%0")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=d")	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")			 (match_operand:SI 2 "general_operand" "di")			 (match_operand:SI 3 "general_operand" "di")))]  "TARGET_68020 && TARGET_BITFIELD"  "bfextu [%c3,%c2]%1,%0")(define_insn ""  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")			 (match_operand:SI 1 "general_operand" "di")			 (match_operand:SI 2 "general_operand" "di"))	(const_int 0))]  "TARGET_68020 && TARGET_BITFIELD"  "*{  CC_STATUS_INIT;  return \"bfclr [%c2,%c1]%0\";}")(define_insn ""  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")			 (match_operand:SI 1 "general_operand" "di")			 (match_operand:SI 2 "general_operand" "di"))	(const_int -1))]  "TARGET_68020 && TARGET_BITFIELD"  "*{  CC_STATUS_INIT;  return \"bfset [%c2,%c1]%0\";}")(define_insn ""  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")			 (match_operand:SI 1 "general_operand" "di")			 (match_operand:SI 2 "general_operand" "di"))	(match_operand:SI 3 "general_operand" "d"))]  "TARGET_68020 && TARGET_BITFIELD"  "*{  return \"bfins %3,[%c2,%c1]%0\";}");; Special patterns for optimizing bit-field instructions.(define_insn ""  [(set (cc0)	(zero_extract:SI (match_operand:QI 0 "memory_operand" "o")			 (match_operand:SI 1 "general_operand" "di")			 (match_operand:SI 2 "general_operand" "di")))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[1]) == CONST_INT"  "*{  if (operands[1] == const1_rtx      && GET_CODE (operands[2]) == CONST_INT)    {          int width = GET_CODE (operands[0]) == REG ? 31 : 7;      return output_btst (operands,			  gen_rtx (CONST_INT, VOIDmode,				   width - INTVAL (operands[2])),			  operands[0],			  insn, 1000);      /* Pass 1000 as SIGNPOS argument so that btst will         not think we are testing the sign bit for an `and'	 and assume that nonzero implies a negative result.  */    }  if (INTVAL (operands[1]) != 32)    cc_status.flags = CC_NOT_NEGATIVE;  return \"bftst [%c2,%c1]%0\";}")(define_insn ""  [(set (cc0)	(subreg:QI	 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")			  (match_operand:SI 1 "general_operand" "di")			  (match_operand:SI 2 "general_operand" "di"))	 0))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[1]) == CONST_INT"  "*{  if (operands[1] == const1_rtx      && GET_CODE (operands[2]) == CONST_INT)    {          int width = GET_CODE (operands[0]) == REG ? 31 : 7;      return output_btst (operands,			  gen_rtx (CONST_INT, VOIDmode,				   width - INTVAL (operands[2])),			  operands[0],			  insn, 1000);      /* Pass 1000 as SIGNPOS argument so that btst will         not think we are testing the sign bit for an `and'	 and assume that nonzero implies a negative result.  */    }  if (INTVAL (operands[1]) != 32)    cc_status.flags = CC_NOT_NEGATIVE;  return \"bftst [%c2,%c1]%0\";}")(define_insn ""  [(set (cc0)	(subreg:HI	 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")			  (match_operand:SI 1 "general_operand" "di")			  (match_operand:SI 2 "general_operand" "di"))	 0))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[1]) == CONST_INT"  "*{  if (operands[1] == const1_rtx      && GET_CODE (operands[2]) == CONST_INT)    {          int width = GET_CODE (operands[0]) == REG ? 31 : 7;      return output_btst (operands,			  gen_rtx (CONST_INT, VOIDmode,				   width - INTVAL (operands[2])),			  operands[0],			  insn, 1000);      /* Pass 1000 as SIGNPOS argument so that btst will         not think we are testing the sign bit for an `and'	 and assume that nonzero implies a negative result.  */    }  if (INTVAL (operands[1]) != 32)    cc_status.flags = CC_NOT_NEGATIVE;  return \"bftst [%c2,%c1]%0\";}")  ;;; now handle the register cases(define_insn ""  [(set (cc0)	(zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")			 (match_operand:SI 1 "general_operand" "di")			 (match_operand:SI 2 "general_operand" "di")))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[1]) == CONST_INT"  "*{  if (operands[1] == const1_rtx      && GET_CODE (operands[2]) == CONST_INT)    {          int width = GET_CODE (operands[0]) == REG ? 31 : 7;      return output_btst (operands,			  gen_rtx (CONST_INT, VOIDmode,				   width - INTVAL (operands[2])),			  operands[0],			  insn, 1000);      /* Pass 1000 as SIGNPOS argument so that btst will         not think we are testing the sign bit for an `and'	 and assume that nonzero implies a negative result.  */    }  if (INTVAL (operands[1]) != 32)    cc_status.flags = CC_NOT_NEGATIVE;  return \"bftst [%c2,%c1]%0\";}")(define_insn ""  [(set (cc0)	(subreg:QI	 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")			  (match_operand:SI 1 "general_operand" "di")			  (match_operand:SI 2 "general_operand" "di"))	 0))]  "TARGET_68020 && TARGET_BITFIELD   && GET_CODE (operands[1]) == CONST_INT"  "*{  if (operands[1] == const1_rtx      && GET_CODE (operands[2]) == CONST_INT)    {          int width = GET_CODE (operands[0]) == REG ? 31 : 7;      return output_btst (operands,			  gen_rtx (CONST_INT, VOIDmode,				   width - INTVAL (operands[2])),			  operands[0],			  insn, 1000);      /* Pass 1000 as SIGNPOS argument so that btst will         not think we are testing the sign bit for an `and'	 and assume that nonzero implies a negative result.  */    }  if (INTVAL (operands[1]) != 32)    cc_status.flags = CC_NOT_NEGATIVE;  return \"bftst [%c2,%c1]%0\";}")(define_insn ""  [(set (cc0)	(subreg:HI	 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")			  (match_operand:SI 1 "general_operand" "di")			  (match_