/* Definitions of target machine for GNU compiler for Intel 80386.   Copyright (C) 1988 Free Software Foundation, Inc.This file is part of GNU CC.GNU CC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 1, or (at your option)any later version.GNU CC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GNU CC; see the file COPYING.  If not, write tothe Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  *//* Note that some other tm- files include this one and then override   many of the definitions that relate to assembler syntax.  *//* Names to predefine in the preprocessor for this target machine.  *//* the file tm-compaq.h includes this file */#define I386 1/* Run-time compilation parameters selecting different hardware subsets.  */extern int target_flags;/* Macros used in the machine description to test the flags.  *//* Compile 80387 insns for floating point (not library calls).  */#define TARGET_80387 (target_flags & 1)/* Compile using ret insn that pops args.   This will not work unless you use prototypes at least   for all functions that can take varying numbers of args.  */  #define TARGET_RTD (target_flags & 8)/* Compile passing first two args in regs 0 and 1.   This exists only to test compiler features that will   be needed for RISC chips.  It is not usable   and is not intended to be usable on this cpu.  */#define TARGET_REGPARM (target_flags & 020)/* Macro to define tables used to set the flags.   This is a list in braces of pairs in braces,   each pair being { "NAME", VALUE }   where VALUE is the bits to set or minus the bits to clear.   An empty string NAME is used to identify the default VALUE.  */#define TARGET_SWITCHES  \  { { "80387", 1},				\    { "soft-float", -1},			\    { "rtd", 8},				\    { "nortd", -8},				\    { "regparm", 020},				\    { "noregparm", -020},			\    { "", TARGET_DEFAULT}}/* TARGET_DEFAULT is defined in tm-compaq.h, etc.  *//* target machine storage layout *//* Define this if most significant byte of a word is the lowest numbered.  *//* That is true on the 80386.  *//* #define BITS_BIG_ENDIAN *//* Define this if most significant byte of a word is the lowest numbered.  *//* That is not true on the 80386.  *//* #define BYTES_BIG_ENDIAN *//* Define this if most significant word of a multiword number is numbered.  *//* Not true for 80386 *//* #define WORDS_BIG_ENDIAN *//* number of bits in an addressible storage unit */#define BITS_PER_UNIT 8/* Width in bits of a "word", which is the contents of a machine register.   Note that this is not necessarily the width of data type `int';   if using 16-bit ints on a 80386, this would still be 32.   But on a machine with 16-bit registers, this would be 16.  */#define BITS_PER_WORD 32/* Width of a word, in units (bytes).  */#define UNITS_PER_WORD 4/* Width in bits of a pointer.   See also the macro `Pmode' defined below.  */#define POINTER_SIZE 32/* Allocation boundary (in *bits*) for storing pointers in memory.  */#define POINTER_BOUNDARY 32/* Allocation boundary (in *bits*) for storing arguments in argument list.  */#define PARM_BOUNDARY 32/* Boundary (in *bits*) on which stack pointer should be aligned.  */#define STACK_BOUNDARY 32/* Allocation boundary (in *bits*) for the code of a function.  */#define FUNCTION_BOUNDARY 32/* Alignment of field after `int : 0' in a structure. */#define EMPTY_FIELD_BOUNDARY 32/* There is no point aligning anything to a rounder boundary than this. *//* Some structures in the ATT libraries are assumed to round up from 16 to 18   bytes, for example the _io_buf */#define BIGGEST_ALIGNMENT 32/* Define this if move instructions will actually fail to work   when given unaligned data.  *//* #define STRICT_ALIGNMENT *//* Standard register usage.  *//* Number of actual hardware registers.   The hardware registers are assigned numbers for the compiler   from 0 to just below FIRST_PSEUDO_REGISTER.   All registers that the compiler knows about must be given numbers,   even those that are not normally considered general registers.   In the 80387 we give the 8 general purpose registers the numbers 0-7,   we assign 6 numbers for floating point registers 8-13,   Note that registers 0-7 can be accessed as a  short or int,   while only 0-3 may be used with mov byte instructions.*/#define FIRST_PSEUDO_REGISTER 10/* 1 for registers that have pervasive standard uses   and are not available for the register allocator.   On the 80386, only the stack pointer is such.  */#define FIXED_REGISTERS \/*ax,ad,ac,ab,si,di,bp,sp,fval,fp0*/       \{  0, 0, 0, 0, 0, 0, 0, 1, 1, 0}/* ;;change-wfs *//* 1 for registers not available across function calls.   These must include the FIXED_REGISTERS and also any   registers that can be used without being saved.   The latter must include the registers where values are returned   and the register where structure-value addresses are passed.   Aside from that, you can include as many other registers as you like.  */#define CALL_USED_REGISTERS \/*ax,ad,ac,ab,si,di,bp,sp,*/ \{  1, 1, 1, 0, 0, 0, 0, 1,  \   1, 1}/* Return number of consecutive hard regs needed starting at reg REGNO   to hold something of mode MODE.   This is ordinarily the length in words of a value of mode MODE   but can be less for certain modes in special long registers.   Actually there are no two word move instructions for consecutive    registers.  And only registers 0-3 may have mov byte instructions   applied to them.   */#define HARD_REGNO_NREGS(REGNO, MODE)   \  ((REGNO) >= 8 ? 1				\   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.   On the 80386, the first 4 cpu registers can hold any mode.   While the floating point registers may hold SFmode or DFmode only.   */#define HARD_REGNO_MODE_OK(REGNO, MODE) \  hard_regno_mode_ok(REGNO,MODE)/* Value is 1 if it is a good idea to tie two pseudo registers   when one has mode MODE1 and one has mode MODE2.   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,   for any hard reg, then this must be 0 for correct output.  */#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))/* Specify the registers used for certain standard purposes.   The values of these macros are register numbers.  *//* on the 386 the pc register is %eip, and is not usable as a general   register.  The ordinary mov instructions won't work *//* #define PC_REGNUM  *//* Register to use for pushing function arguments.  */#define STACK_POINTER_REGNUM 7/* Base register for access to local variables of the function.  */#define FRAME_POINTER_REGNUM 6/* First floating point reg */#define FIRST_FLOAT_REG 8/* Value should be nonzero if functions must have frame pointers.   Zero means the frame pointer need not be set up (and parms   may be accessed via the stack pointer) in functions that seem suitable.   This is computed in `reload', in reload1.c.  */#define FRAME_POINTER_REQUIRED 0/* Base register for access to arguments of the function.  */#define ARG_POINTER_REGNUM 6/* Register in which static-chain is passed to a function.  */#define STATIC_CHAIN_REGNUM 2/* Register in which address to store a structure value   arrives in the function.  On the 386, the prologue   copies this from the stack to register %eax.  */#define STRUCT_VALUE_INCOMING	\   gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, frame_pointer_rtx,	\				 gen_rtx (CONST_INT, VOIDmode, 8)))/* Place in which caller passes the structure value address.   Actually, all that matters about this value is it its rtx_code:   MEM means push the value on the stack like an argument.  */#define STRUCT_VALUE \   gen_rtx (MEM, Pmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx))/* Define the classes of registers for register constraints in the   machine description.  Also define ranges of constants.   One of the classes must always be named ALL_REGS and include all hard regs.   If there is more than one class, another class must be named NO_REGS   and contain no registers.   The name GENERAL_REGS must be the name of a class (or an alias for   another name such as ALL_REGS).  This is the class of registers   that is allowed by "g" or "r" in a register constraint.   Also, registers outside this class are allocated only when   instructions express preferences for them.   The classes must be numbered in nondecreasing order; that is,   a larger-numbered class must never be contained completely   in a smaller-numbered class.   For any two classes, it is very desirable that there be another   class that represents their union.  */   enum reg_class {  NO_REGS, AREG, DREG, ADREG, CREG, BREG, Q_REGS, SIREG, DIREG,  INDEX_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES };#define N_REG_CLASSES (int) LIM_REG_CLASSES/* Give names of register classes as strings for dump file.   */#define REG_CLASS_NAMES \{  "NO_REGS", "AREG", "DREG", "ADREG", "CREG", "BREG","Q_REGS", \   "SIREG", "DIREG",						\   "INDEX_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS"}/* Define which registers fit in which classes.   This is an initializer for a vector of HARD_REG_SET   of length N_REG_CLASSES.  */#define REG_CLASS_CONTENTS {0, 0x1, 0x2, 0x3, 0x4, 0x8, 0xf,\			    0x10, 0x20, 0x7f, 0xff, 0x300, 0x3ff}/* The same information, inverted:   Return the class number of the smallest class containing   reg number REGNO.  This could be a conditional expression   or could index an array.  */#define REGNO_REG_CLASS(REGNO) \ ((REGNO) == 0 ? AREG : \  (REGNO) == 1 ? DREG : \  (REGNO) == 2 ? CREG : \  (REGNO) == 3 ? BREG : \  (REGNO) == 4 ? SIREG : \  (REGNO) == 5 ? DIREG : \  (REGNO) == 7 ? GENERAL_REGS : \  (REGNO) < 8 ? INDEX_REGS : \  FLOAT_REGS)#define NON_QI_REG_P(X) \  (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))#define FP_REGNO_P(n) ((n) >= FIRST_FLOAT_REG && (n) < FIRST_PSEUDO_REGISTER)/* This definition indicates that some register classes are very small,   which requires extra care in certain optimizations.  */#define SMALL_REGISTER_CLASSES/* Try to maintain the accuracy of the death notes for regs satisfying the   following.  Important for stack like regs, to know when to pop. */#define PRESERVE_DEATH_INFO_REGNO_P(x) FP_REGNO_P(x)/* 1 if register REGNO can magically overlap other regs.   Note that nonzero values work only in very special circumstances.   We return 1 for an FP reg because "both" our FP regs   are really the same reg.  */#define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO)/* The class value for index registers, and the one for base regs.  */#define INDEX_REG_CLASS INDEX_REGS#define BASE_REG_CLASS GENERAL_REGS/* Get reg_class from a letter such as appears in the machine description.  */#define REG_CLASS_FROM_LETTER(C)		\  ((C) == 'r' ? GENERAL_REGS :			\   (C) == 'q' ? Q_REGS :			\   (C) == 'f' ? FLOAT_REGS :			\   (C) == 'a' ? AREG : (C) == 'b' ? BREG :	\   (C) == 'c' ? CREG : (C) == 'd' ? DREG :	\   (C) == 'A' ? ADREG :				\   (C) == 'S' ? SIREG :				\   (C) == 'D' ? DIREG : NO_REGS)/* The letters I, J, K, L and M in a register constraint string   can be used to stand for particular ranges of immediate operands.   This macro defines what the ranges are.   C is the letter, and VALUE is a constant value.   Return 1 if VALUE is in the range specified by C.   I is for the maximum shifts.    */#define CONST_OK_FOR_LETTER_P(VALUE, C)  \  ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 :0)/* Similar, but for floating constants, and defining letters G and H.   Here VALUE is the CONST_DOUBLE rtx itself.  */#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)  \  ((C) == 'G' ? ! (TARGET_80387 && standard_80387_constant_p (VALUE)) : 1)/* Given an rtx X being reloaded into a reg required to be   in class CLASS, return the class of reg to actually use.   In general this is just CLASS; but on some machines   in some cases it is preferable to use a more restrictive class.   On the 80386 series, we prevent floating constants from being   reloaded into floating registers (since no move-insn can do that)   and we ensure that QImodes aren't reloaded into the esi or edi reg.  */#define PREFERRED_RELOAD_CLASS(X,CLASS)			\  (GET_CODE (X) == CONST_DOUBLE				\   ? ((CLASS) == GENERAL_REGS || (CLASS) == ALL_REGS	\      ? GENERAL_REGS : NO_REGS)				\   : GET_MODE (X) == QImode				\   ? ((CLASS) == GENERAL_REGS || (CLASS) == ALL_REGS	\      ? Q_REGS						\      : (CLASS) == INDEX_REGS ? (abort (), INDEX_REGS)	\      : (CLASS))					\   : (CLASS))/* Return the maximum number of consecutive registers   needed to represent mode MODE in a register of class CLASS.  *//* On the 80386, this is the size of MODE in words,