/* Definitions of target machine for GNU compiler.  Sun 68000/68020 version.   Copyright (C) 1987, 1988 Free Software Foundation, Inc.This file is part of GNU CC.GNU CC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 1, or (at your option)any later version.GNU CC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GNU CC; see the file COPYING.  If not, write tothe Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  *//* Note that some other tm- files include this one and then override   many of the definitions that relate to assembler syntax.  *//* Names to predefine in the preprocessor for this target machine.  *//* See tm-sun3.h, tm-sun2.h, tm-isi68.h for different CPP_PREDEFINES.  *//* Print subsidiary information on the compiler version in use.  */#ifdef MOTOROLA#define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");#else#define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");#endif/* Run-time compilation parameters selecting different hardware subsets.  */extern int target_flags;/* Macros used in the machine description to test the flags.  *//* Compile for a 68020 (not a 68000 or 68010).  */#define TARGET_68020 (target_flags & 1)/* Compile 68881 insns for floating point (not library calls).  */#define TARGET_68881 (target_flags & 2)/* Compile using 68020 bitfield insns.  */#define TARGET_BITFIELD (target_flags & 4)/* Compile using rtd insn calling sequence.   This will not work unless you use prototypes at least   for all functions that can take varying numbers of args.  */#define TARGET_RTD (target_flags & 8)/* Compile passing first two args in regs 0 and 1.   This exists only to test compiler features that will   be needed for RISC chips.  It is not usable   and is not intended to be usable on this cpu.  */#define TARGET_REGPARM (target_flags & 020)/* Compile with 16-bit `int'.  */#define TARGET_SHORT (target_flags & 040)/* Compile with special insns for Sun FPA.  */#define TARGET_FPA (target_flags & 0100)/* Macro to define tables used to set the flags.   This is a list in braces of pairs in braces,   each pair being { "NAME", VALUE }   where VALUE is the bits to set or minus the bits to clear.   An empty string NAME is used to identify the default VALUE.  */#define TARGET_SWITCHES  \  { { "68020", 5},				\    { "c68020", 5},				\    { "68881", 2},				\    { "bitfield", 4},				\    { "68000", -5},				\    { "c68000", -5},				\    { "soft-float", -0102},			\    { "nobitfield", -4},			\    { "rtd", 8},				\    { "nortd", -8},				\    { "short", 040},				\    { "noshort", -040},				\    { "fpa", 0100},				\    { "nofpa", -0100},				\    { "", TARGET_DEFAULT}}/* TARGET_DEFAULT is defined in tm-sun*.h and tm-isi68.h, etc.  *//* Blow away 68881 flag silently on TARGET_FPA (since we can't clear   any bits in TARGET_SWITCHES above) */#define OVERRIDE_OPTIONS		\{					\  if (TARGET_FPA) target_flags &= ~2;	\}/* target machine storage layout *//* Define this if most significant bit is lowest numbered   in instructions that operate on numbered bit-fields.   This is true for 68020 insns such as bfins and bfexts.   We make it true always by avoiding using the single-bit insns   except in special cases with constant bit numbers.  */#define BITS_BIG_ENDIAN/* Define this if most significant byte of a word is the lowest numbered.  *//* That is true on the 68000.  */#define BYTES_BIG_ENDIAN/* Define this if most significant word of a multiword number is numbered.  *//* For 68000 we can decide arbitrarily   since there are no machine instructions for them.  *//* #define WORDS_BIG_ENDIAN *//* number of bits in an addressible storage unit */#define BITS_PER_UNIT 8/* Width in bits of a "word", which is the contents of a machine register.   Note that this is not necessarily the width of data type `int';   if using 16-bit ints on a 68000, this would still be 32.   But on a machine with 16-bit registers, this would be 16.  */#define BITS_PER_WORD 32/* Width of a word, in units (bytes).  */#define UNITS_PER_WORD 4/* Width in bits of a pointer.   See also the macro `Pmode' defined below.  */#define POINTER_SIZE 32/* Allocation boundary (in *bits*) for storing pointers in memory.  */#define POINTER_BOUNDARY 16/* Allocation boundary (in *bits*) for storing arguments in argument list.  */#define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)/* Boundary (in *bits*) on which stack pointer should be aligned.  */#define STACK_BOUNDARY 16/* Allocation boundary (in *bits*) for the code of a function.  */#define FUNCTION_BOUNDARY 16/* Alignment of field after `int : 0' in a structure.  */#define EMPTY_FIELD_BOUNDARY 16/* No data type wants to be aligned rounder than this.  */#define BIGGEST_ALIGNMENT 16/* Define this if move instructions will actually fail to work   when given unaligned data.  */#define STRICT_ALIGNMENT/* Define number of bits in most basic integer type.   (If undefined, default is BITS_PER_WORD).  */#define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)/* Standard register usage.  *//* Number of actual hardware registers.   The hardware registers are assigned numbers for the compiler   from 0 to just below FIRST_PSEUDO_REGISTER.   All registers that the compiler knows about must be given numbers,   even those that are not normally considered general registers.   For the 68000, we give the data registers numbers 0-7,   the address registers numbers 010-017,   and the 68881 floating point registers numbers 020-027.  */#define FIRST_PSEUDO_REGISTER 56 /* 24 *//* 1 for registers that have pervasive standard uses   and are not available for the register allocator.   On the 68000, only the stack pointer is such.  *//* fpa0 is also reserved so that it can be used to move shit back and   forth between high fpa regs and everything else. */#define FIXED_REGISTERS  \ {0, 0, 0, 0, 0, 0, 0, 0, \  0, 0, 0, 0, 0, 0, 0, 1, \  0, 0, 0, 0, 0, 0, 0, 0, \  /* FPA registers.  */   \  1, 0, 0, 0, 0, 0, 0, 0, \  0, 0, 0, 0, 0, 0, 0, 0, \  0, 0, 0, 0, 0, 0, 0, 0, \  0, 0, 0, 0, 0, 0, 0, 0, }/* 1 for registers not available across function calls.   These must include the FIXED_REGISTERS and also any   registers that can be used without being saved.   The latter must include the registers where values are returned   and the register where structure-value addresses are passed.   Aside from that, you can include as many other registers as you like.  */#define CALL_USED_REGISTERS \ {1, 1, 0, 0, 0, 0, 0, 0, \  1, 1, 0, 0, 0, 0, 0, 1, \  1, 1, 0, 0, 0, 0, 0, 0, \  /* FPA registers.  */   \  1, 1, 1, 1, 0, 0, 0, 0, \  0, 0, 0, 0, 0, 0, 0, 0, \  0, 0, 0, 0, 0, 0, 0, 0, \  0, 0, 0, 0, 0, 0, 0, 0, }/* Make sure everything's fine if we *don't* have a given processor.   This assumes that putting a register in fixed_regs will keep the   compilers mitt's completely off it.  We don't bother to zero it out   of register classes.  If neither TARGET_FPA or TARGET_68881 is set,   the compiler won't touch since no instructions that use these   registers will be valid.  */#define CONDITIONAL_REGISTER_USAGE \{ 						\  int i; 					\  HARD_REG_SET x; 				\  if (!TARGET_FPA)				\    { 						\      COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \       if (TEST_HARD_REG_BIT (x, i)) 		\	fixed_regs[i] = call_used_regs[i] = 1; 	\    } 						\  if (TARGET_FPA)				\    { 						\      COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \       if (TEST_HARD_REG_BIT (x, i)) 		\	fixed_regs[i] = call_used_regs[i] = 1; 	\    } 						\}/* Return number of consecutive hard regs needed starting at reg REGNO   to hold something of mode MODE.   This is ordinarily the length in words of a value of mode MODE   but can be less for certain modes in special long registers.   On the 68000, ordinary registers hold 32 bits worth;   for the 68881 registers, a single register is always enough for   anything that can be stored in them at all.  */#define HARD_REGNO_NREGS(REGNO, MODE)   \  ((REGNO) >= 16 ? 1				\   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.   On the 68000, the cpu registers can hold any mode but the 68881 registers   can hold only SFmode or DFmode.  And the 68881 registers can't hold anything   if 68881 use is disabled.  However, the Sun FPA register can   (apparently) hold whatever you feel like putting in them.  */#define HARD_REGNO_MODE_OK(REGNO, MODE) \  (((REGNO) < 16 &&						\    (!TARGET_FPA || (MODE) != DFmode || (REGNO) != 7))		\   || ((REGNO) < 24						\       ? TARGET_68881 && ((MODE) == SFmode || (MODE) == DFmode)	\       : ((REGNO) < 56						\	  ? TARGET_FPA : 0)))/* Value is 1 if it is a good idea to tie two pseudo registers   when one has mode MODE1 and one has mode MODE2.   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,   for any hard reg, then this must be 0 for correct output.  */#define MODES_TIEABLE_P(MODE1, MODE2)			\  (! TARGET_68881					\   || (((MODE1) == SFmode || (MODE1) == DFmode)		\       == ((MODE2) == SFmode || (MODE2) == DFmode)))/* Specify the registers used for certain standard purposes.   The values of these macros are register numbers.  *//* m68000 pc isn't overloaded on a register.  *//* #define PC_REGNUM  *//* Register to use for pushing function arguments.  */#define STACK_POINTER_REGNUM 15/* Base register for access to local variables of the function.  */#define FRAME_POINTER_REGNUM 14/* Value should be nonzero if functions must have frame pointers.   Zero means the frame pointer need not be set up (and parms   may be accessed via the stack pointer) in functions that seem suitable.   This is computed in `reload', in reload1.c.  */#define FRAME_POINTER_REQUIRED 0/* Base register for access to arguments of the function.  */#define ARG_POINTER_REGNUM 14/* Register in which static-chain is passed to a function.  */#define STATIC_CHAIN_REGNUM 8/* Register in which address to store a structure value   is passed to a function.  */#define STRUCT_VALUE_REGNUM 9/* Define the classes of registers for register constraints in the   machine description.  Also define ranges of constants.   One of the classes must always be named ALL_REGS and include all hard regs.   If there is more than one class, another class must be named NO_REGS   and contain no registers.   The name GENERAL_REGS must be the name of a class (or an alias for   another name such as ALL_REGS).  This is the class of registers   that is allowed by "g" or "r" in a register constraint.   Also, registers outside this class are allocated only when   instructions express preferences for them.   The classes must be numbered in nondecreasing order; that is,   a larger-numbered class must never be contained completely   in a smaller-numbered class.   For any two classes, it is very desirable that there be another   class that represents their union.  *//* The 68000 has three kinds of registers, so eight classes would be   a complete set.  One of them is not needed.  *//* * Notes on final choices: * *   1) Didn't feel any need to union-ize LOW_FPA_REGS with anything * else. *   2) Removed all unions that involve address registers with * floating point registers (left in unions of address and data with * floating point). *   3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. *   4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. *   4) Left in everything else. */enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,  FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,  DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,  GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,  LIM_REG_CLASSES };#define N_REG_CLASSES (int) LIM_REG_CLASSES/* Give names of register classes as strings for dump file.   */