operands[3] = gen_reg_rtx (SImode);  operands[4] = force_reg (SImode, gen_rtx (CONST_INT, VOIDmode, 65535));  operands[5] = force_reg (SImode, gen_rtx (CONST_INT, VOIDmode, -32768));}")(define_expand "extendqihi2"  [(set (match_dup 2)	(and:HI (match_operand:QI 1 "register_operand" "") ;Changed to SI below		(const_int 255)))   (set (match_dup 3)	(plus:SI (match_dup 2) (const_int -128)))   (set (match_operand:HI 0 "register_operand" "")	(xor:SI (match_dup 3) (const_int -128)))]  ""  "{  if (GET_CODE (operands[1]) == SUBREG)    operands[1] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[1]),			   SUBREG_WORD (operands[1]));  else    operands[1] = gen_rtx (SUBREG, HImode, operands[1], 0);  operands[2] = gen_reg_rtx (HImode);  operands[3] = gen_reg_rtx (HImode);}")(define_expand "extendqisi2"  [(set (match_dup 2)	(and:SI (match_operand:QI 1 "register_operand" "") ;Changed to SI below		(const_int 255)))   (set (match_dup 3) (plus:SI (match_dup 2) (const_int -128)))   (set (match_operand:SI 0 "register_operand" "")	(xor:SI (match_dup 3) (const_int -128)))]  ""  "{  if (GET_CODE (operands[1]) == SUBREG)    operands[1] = gen_rtx (SUBREG, SImode, SUBREG_REG (operands[1]),			   SUBREG_WORD (operands[1]));  else    operands[1] = gen_rtx (SUBREG, SImode, operands[1], 0);  operands[2] = gen_reg_rtx (SImode);  operands[3] = gen_reg_rtx (SImode);}");;- arithmetic instructions(define_insn "addsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r")		 (match_operand:SI 2 "nonmemory_operand" "rI")))]  ""  "add %0,%1,%2")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r")		 (match_operand:SI 2 "big_immediate_operand" "g")))]  "GET_CODE (operands[2]) == CONST_INT    && (unsigned) (INTVAL (operands[2]) + 0x8000000) < 0x10000000"  "*{  return     output_add_large_offset (operands[0], operands[1], INTVAL (operands[2]));}")(define_insn "subsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(minus:SI (match_operand:SI 1 "register_operand" "r")		  (match_operand:SI 2 "nonmemory_operand" "rI")))]  ""  "sub %0,%1,%2")(define_insn "andsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(and:SI (match_operand:SI 1 "nonmemory_operand" "%r")		(match_operand:SI 2 "nonmemory_operand" "rI")))]  ""  "and %0,%1,%2")(define_insn "iorsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(ior:SI (match_operand:SI 1 "nonmemory_operand" "%r")		(match_operand:SI 2 "nonmemory_operand" "rI")))]  ""  "or %0,%1,%2")(define_insn "xorsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(xor:SI (match_operand:SI 1 "nonmemory_operand" "%r")		(match_operand:SI 2 "nonmemory_operand" "rI")))]  ""  "xor %0,%1,%2")(define_insn "negsi2"  [(set (match_operand:SI 0 "register_operand" "=r")	(neg:SI (match_operand:SI 1 "nonmemory_operand" "rI")))]  ""  "sub %0,r0,%1")(define_insn "one_cmplsi2"  [(set (match_operand:SI 0 "register_operand" "=r")	(not:SI (match_operand:SI 1 "register_operand" "r")))]  ""  "xor %0,%1,$-1");; Floating point arithmetic instructions.(define_insn "adddf3"  [(set (match_operand:DF 0 "register_operand" "=f")	(plus:DF (match_operand:DF 1 "register_operand" "f")		 (match_operand:DF 2 "register_operand" "f")))]  "TARGET_FPU"  "fadd %0,%1,%2")(define_insn "addsf3"  [(set (match_operand:SF 0 "register_operand" "=f")	(plus:SF (match_operand:SF 1 "register_operand" "f")		 (match_operand:SF 2 "register_operand" "f")))]  "TARGET_FPU"  "fadd %0,%1,%2")(define_insn "subdf3"  [(set (match_operand:DF 0 "register_operand" "=f")	(minus:DF (match_operand:DF 1 "register_operand" "f")		  (match_operand:DF 2 "register_operand" "f")))]  "TARGET_FPU"  "fsub %0,%1,%2")(define_insn "subsf3"  [(set (match_operand:SF 0 "register_operand" "=f")	(minus:SF (match_operand:SF 1 "register_operand" "f")		  (match_operand:SF 2 "register_operand" "f")))]  "TARGET_FPU"  "fsub %0,%1,%2")(define_insn "muldf3"  [(set (match_operand:DF 0 "register_operand" "=f")	(mult:DF (match_operand:DF 1 "register_operand" "f")		 (match_operand:DF 2 "register_operand" "f")))]  "TARGET_FPU"  "fmul %0,%1,%2")(define_insn "mulsf3"  [(set (match_operand:SF 0 "register_operand" "=f")	(mult:SF (match_operand:SF 1 "register_operand" "f")		 (match_operand:SF 2 "register_operand" "f")))]  "TARGET_FPU"  "fmul %0,%1,%2")(define_insn "divdf3"  [(set (match_operand:DF 0 "register_operand" "=f")	(div:DF (match_operand:DF 1 "register_operand" "f")		(match_operand:DF 2 "register_operand" "f")))]  "TARGET_FPU"  "fdiv %0,%1,%2")(define_insn "divsf3"  [(set (match_operand:SF 0 "register_operand" "=f")	(div:SF (match_operand:SF 1 "register_operand" "f")		(match_operand:SF 2 "register_operand" "f")))]  "TARGET_FPU"  "fdiv %0,%1,%2")(define_insn "negdf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(neg:DF (match_operand:DF 1 "nonmemory_operand" "f")))]  "TARGET_FPU"  "fneg %0,%1")(define_insn "negsf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(neg:SF (match_operand:SF 1 "nonmemory_operand" "f")))]  "TARGET_FPU"  "fneg %0,%1")(define_insn "absdf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(abs:DF (match_operand:DF 1 "nonmemory_operand" "f")))]  "TARGET_FPU"  "fabs %0,%1")(define_insn "abssf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(abs:SF (match_operand:SF 1 "nonmemory_operand" "f")))]  "TARGET_FPU"  "fabs %0,%1");; Shift instructions(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(ashift:SI (match_operand:SI 1 "register_operand" "r")		   (match_operand:SI 2 "immediate_operand" "I")))]  "GET_CODE (operands[2]) == CONST_INT"  "*{  unsigned int amount = INTVAL (operands[2]);  switch (amount)    {    case 0:      return \"add_nt %0,%1,$0\";    case 1:      return \"sll %0,%1,$1\";    case 2:      return \"sll %0,%1,$2\";    default:      output_asm_insn (\"sll %0,%1,$3\", operands);      for (amount -= 3; amount >= 3; amount -= 3)	output_asm_insn (\"sll %0,%0,$3\", operands);      if (amount > 0)	output_asm_insn (amount == 1 ? \"sll %0,%0,$1\" : \"sll %0,%0,$2\",			 operands);      return \"\";    }}")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")	             (match_operand:SI 2 "immediate_operand" "I")))]  "GET_CODE (operands[2]) == CONST_INT"  "*{  unsigned int amount = INTVAL (operands[2]);  if (amount == 0)     return \"add_nt %0,%1,$0\";  else    output_asm_insn (\"sra %0,%1,$1\", operands);    for (amount -= 1; amount > 0; amount -= 1)    output_asm_insn (\"sra %0,%0,$1\", operands);  return \"\";}")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")	             (match_operand:SI 2 "immediate_operand" "I")))]  "GET_CODE (operands[2]) == CONST_INT"  "*{  unsigned int amount = INTVAL (operands[2]);  if (amount == 0)     return \"add_nt %0,%1,$0\";  else    output_asm_insn (\"srl %0,%1,$1\", operands);    for (amount -= 1; amount > 0; amount -= 1)    output_asm_insn (\"srl %0,%0,$1\", operands);  return \"\";}")(define_expand "ashlsi3"  [(set (match_operand:SI 0 "register_operand" "")	(ashift:SI (match_operand:SI 1 "register_operand" "")		   (match_operand:SI 2 "nonmemory_operand" "")))]  ""  "{  if (GET_CODE (operands[2]) != CONST_INT      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 3))    FAIL;}")(define_expand "lshlsi3"  [(set (match_operand:SI 0 "register_operand" "")	(ashift:SI (match_operand:SI 1 "register_operand" "")		   (match_operand:SI 2 "nonmemory_operand" "")))]  ""  "{  if (GET_CODE (operands[2]) != CONST_INT      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 3))    FAIL;}")(define_expand "ashrsi3"  [(set (match_operand:SI 0 "register_operand" "")	(ashiftrt:SI (match_operand:SI 1 "register_operand" "")		     (match_operand:SI 2 "nonmemory_operand" "")))]  ""  "{  if (GET_CODE (operands[2]) != CONST_INT      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 1))    FAIL;}")(define_expand "lshrsi3"  [(set (match_operand:SI 0 "register_operand" "")	(lshiftrt:SI (match_operand:SI 1 "register_operand" "")		     (match_operand:SI 2 "nonmemory_operand" "")))]  ""  "{  if (GET_CODE (operands[2]) != CONST_INT      || (! TARGET_EXPAND_SHIFTS && (unsigned) INTVAL (operands[2]) > 1))    FAIL;}");; Unconditional and other jump instructions(define_insn "jump"  [(set (pc)	(label_ref (match_operand 0 "" "")))]  ""  "jump %l0\;nop")(define_insn "tablejump"  [(set (pc) (match_operand:SI 0 "register_operand" "r"))   (use (label_ref (match_operand 1 "" "")))]  ""  "jump_reg r0,%0\;nop");;- jump to subroutine(define_insn "call"  [(call (match_operand:SI 0 "memory_operand" "m")	 (match_operand:SI 1 "general_operand" "g"))]  ;;- Don't use operand 1 for most machines.  ""  "add_nt r2,%0\;call .+8\;jump_reg r0,r2\;nop")(define_insn "call_value"  [(set (match_operand 0 "" "=g")	(call (match_operand:SI 1 "memory_operand" "m")	      (match_operand:SI 2 "general_operand" "g")))]  ;;- Don't use operand 1 for most machines.  ""  "add_nt r2,%1\;call .+8\;jump_reg r0,r2\;nop");; A memory ref with constant address is not normally valid.;; But it is valid in a call insns.  This pattern allows the;; loading of the address to combine with the call.(define_insn ""  [(call (mem:SI (match_operand:SI 0 "" "i"))	 (match_operand:SI 1 "general_operand" "g"))]  ;;- Don't use operand 1 for most machines.  "GET_CODE (operands[0]) == SYMBOL_REF"  "call %0\;nop")(define_insn ""  [(set (match_operand 0 "" "=g")	(call (mem:SI (match_operand:SI 1 "" "i"))	      (match_operand:SI 2 "general_operand" "g")))]  ;;- Don't use operand 1 for most machines.  "GET_CODE (operands[1]) == SYMBOL_REF"  "call %1\;nop")(define_insn "nop"  [(const_int 0)]  ""  "nop");;- Local variables:;;- mode:emacs-lisp;;- comment-start: ";;- ";;- eval: (set-syntax-table (copy-sequence (syntax-table)));;- eval: (modify-syntax-entry ?[ "(]");;- eval: (modify-syntax-entry ?] ")[");;- eval: (modify-syntax-entry ?{ "(}");;- eval: (modify-syntax-entry ?} "){");;- End: