if (code == CODE_FOR_cmpsi)    emit_insn (gen_cmpeqsi (recog_operand[0], recog_operand[1]));  else if (code == CODE_FOR_cmpsf)    emit_insn (gen_cmpeqsf (recog_operand[0], recog_operand[1]));  else if (code == CODE_FOR_cmpdf)    emit_insn (gen_cmpeqdf (recog_operand[0], recog_operand[1]));  else    abort ();  emit_jump_insn (gen_inverse_cbranch (label));  DONE;}")(define_expand "bgt"  [(set (pc)	(if_then_else (gt (cc0)			  (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "{  rtx label = operands[0];  enum insn_code code;  rtx prev;  end_sequence ();  prev = get_last_insn ();  code = recog_memoized (prev);  insn_extract (prev);  NEXT_INSN (PREV_INSN (prev)) = 0;  set_last_insn (PREV_INSN (prev));  start_sequence ();  if (code == CODE_FOR_cmpsi)    emit_insn (gen_cmpgtsi (recog_operand[0], recog_operand[1]));  else if (code == CODE_FOR_cmpsf)    emit_insn (gen_cmpgtsf (recog_operand[0], recog_operand[1]));  else if (code == CODE_FOR_cmpdf)    emit_insn (gen_cmpgtdf (recog_operand[0], recog_operand[1]));  else    abort ();  emit_jump_insn (gen_cbranch (label));  DONE;}")(define_expand "blt"  [(set (pc)	(if_then_else (lt (cc0)			  (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "{  rtx label = operands[0];  enum insn_code code;  rtx prev;  end_sequence ();  prev = get_last_insn ();  code = recog_memoized (prev);  insn_extract (prev);  NEXT_INSN (PREV_INSN (prev)) = 0;  set_last_insn (PREV_INSN (prev));  start_sequence ();  if (code == CODE_FOR_cmpsi)    emit_insn (gen_cmpltsi (recog_operand[0], recog_operand[1]));  else if (code == CODE_FOR_cmpsf)    emit_insn (gen_cmpltsf (recog_operand[0], recog_operand[1]));  else if (code == CODE_FOR_cmpdf)    emit_insn (gen_cmpltdf (recog_operand[0], recog_operand[1]));  else    abort ();  emit_jump_insn (gen_cbranch (label));  DONE;}")(define_expand "ble"  [(set (pc)	(if_then_else (le (cc0)			  (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "{  rtx label = operands[0];  enum insn_code code;  rtx prev;  end_sequence ();  prev = get_last_insn ();  code = recog_memoized (prev);  insn_extract (prev);  NEXT_INSN (PREV_INSN (prev)) = 0;  set_last_insn (PREV_INSN (prev));  start_sequence ();  if (code == CODE_FOR_cmpsi)    {      emit_insn (gen_cmpgtsi (recog_operand[0], recog_operand[1]));      emit_jump_insn (gen_inverse_cbranch (label));    }  else    {      if (code == CODE_FOR_cmpsf)	emit_insn (gen_cmplesf (recog_operand[0], recog_operand[1]));      else if (code == CODE_FOR_cmpdf)	emit_insn (gen_cmpledf (recog_operand[0], recog_operand[1]));      else	abort ();      emit_jump_insn (gen_cbranch (label));    }  DONE;}")(define_expand "bge"  [(set (pc)	(if_then_else (ge (cc0)			  (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "{  rtx label = operands[0];  enum insn_code code;  rtx prev;  end_sequence ();  prev = get_last_insn ();  code = recog_memoized (prev);  insn_extract (prev);  NEXT_INSN (PREV_INSN (prev)) = 0;  set_last_insn (PREV_INSN (prev));  start_sequence ();  if (code == CODE_FOR_cmpsi)    {      emit_insn (gen_cmpltsi (recog_operand[0], recog_operand[1]));      emit_jump_insn (gen_inverse_cbranch (label));    }  else    {      if (code == CODE_FOR_cmpsf)	emit_insn (gen_cmpgesf (recog_operand[0], recog_operand[1]));      else if (code == CODE_FOR_cmpdf)	emit_insn (gen_cmpgedf (recog_operand[0], recog_operand[1]));      else        abort ();      emit_jump_insn (gen_cbranch (label));    }  DONE;}")(define_expand "bgtu"  [(set (pc)	(if_then_else (gtu (cc0)			   (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "{  rtx label = operands[0];  enum insn_code code;  rtx prev;  end_sequence ();  prev = get_last_insn ();  code = recog_memoized (prev);  insn_extract (prev);  NEXT_INSN (PREV_INSN (prev)) = 0;  set_last_insn (PREV_INSN (prev));  start_sequence ();  if (code == CODE_FOR_cmpsi)    emit_insn (gen_cmpleusi (recog_operand[0], recog_operand[1]));  else    abort ();  emit_jump_insn (gen_inverse_cbranch (label));  DONE;}")(define_expand "bltu"  [(set (pc)	(if_then_else (ltu (cc0)			   (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "{  rtx label = operands[0];  enum insn_code code;  rtx prev;  end_sequence ();  prev = get_last_insn ();  code = recog_memoized (prev);  insn_extract (prev);  NEXT_INSN (PREV_INSN (prev)) = 0;  set_last_insn (PREV_INSN (prev));  start_sequence ();  if (code == CODE_FOR_cmpsi)    emit_insn (gen_cmpgeusi (recog_operand[0], recog_operand[1]));  else    abort ();  emit_jump_insn (gen_inverse_cbranch (label));  DONE;}")(define_expand "bgeu"  [(set (pc)	(if_then_else (geu (cc0)			   (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "{  rtx label = operands[0];  enum insn_code code;  rtx prev;  end_sequence ();  prev = get_last_insn ();  code = recog_memoized (prev);  insn_extract (prev);  NEXT_INSN (PREV_INSN (prev)) = 0;  set_last_insn (PREV_INSN (prev));  start_sequence ();  if (code == CODE_FOR_cmpsi)    emit_insn (gen_cmpgeusi (recog_operand[0], recog_operand[1]));  else    abort ();  emit_jump_insn (gen_cbranch (label));  DONE;}")(define_expand "bleu"  [(set (pc)	(if_then_else (leu (cc0)			   (const_int 0))		      (label_ref (match_operand 0 "" ""))		      (pc)))]  ""  "{  rtx label = operands[0];  enum insn_code code;  rtx prev;  end_sequence ();  prev = get_last_insn ();  code = recog_memoized (prev);  insn_extract (prev);  NEXT_INSN (PREV_INSN (prev)) = 0;  set_last_insn (PREV_INSN (prev));  start_sequence ();  if (code == CODE_FOR_cmpsi)    emit_insn (gen_cmpleusi (recog_operand[0], recog_operand[1]));  else    abort ();  emit_jump_insn (gen_cbranch (label));  DONE;}");; Move instructions(define_insn "movsi"  [(set (match_operand:SI 0 "general_operand" "=r,m,f")	(match_operand:SI 1 "general_operand" "rmif,rfJ,rmfJ"))]  ""  "*{  if (GET_CODE (operands[0]) == MEM)    {      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))	return output_store (operands);      if (FP_REG_P (operands[1]))	return \"fst.l %1,%0\";      return \"st.l %r1,%0\";    }  if (GET_CODE (operands[1]) == MEM)    {      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))	return output_load (operands);      if (FP_REG_P (operands[0]))	return \"fld.l %1,%0\";      return \"ld.l %1,%0\";    }  if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))    return \"fmov.ss %1,%0\";  if (FP_REG_P (operands[1]))    return \"fxfr %1,%0\";  if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)    return \"fmov.ss f0,%0\";  if (FP_REG_P (operands[0]))    return \"ixfr %1,%0\";  return \"mov %1,%0\";}")(define_insn "movhi"  [(set (match_operand:HI 0 "general_operand" "=r,m,!*f,!r")	(match_operand:HI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]  ""  "*{  if (GET_CODE (operands[0]) == MEM)    {      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))	return output_store (operands);      return \"st.s %r1,%0\";    }  if (GET_CODE (operands[1]) == MEM)    {      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))	return output_load (operands);      return \"ld.s %1,%0\";    }  if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))    return \"fmov.ss %1,%0\";  if (FP_REG_P (operands[1]))    return \"fxfr %1,%0\";  if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)    return \"fmov.ss f0,%0\";  if (FP_REG_P (operands[0]))    return \"ixfr %1,%0\";  return \"mov %1,%0\";}")(define_insn "movqi"  [(set (match_operand:QI 0 "general_operand" "=r,m,!*f,!r")	(match_operand:QI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]  ""  "*{  if (GET_CODE (operands[0]) == MEM)    {      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))	return output_store (operands);      return \"st.b %r1,%0\";    }  if (GET_CODE (operands[1]) == MEM)    {      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))	return output_load (operands);      return \"ld.b %1,%0\";    }  if (FP_REG_P (operands[1]) && FP_REG_P (operands[0]))    return \"fmov.ss %1,%0\";  if (FP_REG_P (operands[1]))    return \"fxfr %1,%0\";  if (FP_REG_P (operands[0]) && operands[1] == const0_rtx)    return \"fmov.ss f0,%0\";  if (FP_REG_P (operands[0]))    return \"ixfr %1,%0\";  return \"mov %1,%0\";}");; The definition of this insn does not really explain what it does,;; but it should suffice;; that anything generated as this insn will be recognized as one;; and that it won't successfully combine with anything.(define_expand "movstrsi"  [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))		   (mem:BLK (match_operand:BLK 1 "general_operand" "")))	      (use (match_operand:SI 2 "nonmemory_operand" ""))	      (use (match_operand:SI 3 "immediate_operand" ""))	      (clobber (match_dup 4))	      (clobber (match_dup 5))	      (clobber (match_dup 6))	      (clobber (match_dup 0))	      (clobber (match_dup 1))])]  ""  "{  operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));  operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));  operands[4] = gen_reg_rtx (SImode);  operands[5] = gen_reg_rtx (SImode);  operands[6] = gen_reg_rtx (SImode);}")(define_insn ""  [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))	(mem:BLK (match_operand:SI 1 "register_operand" "r")))   (use (match_operand:SI 2 "nonmemory_operand" "rn"))   (use (match_operand:SI 3 "immediate_operand" "i"))   (clobber (match_operand:SI 4 "register_operand" "=r"))   (clobber (match_operand:SI 5 "register_operand" "=r"))   (clobber (match_operand:SI 6 "register_operand" "=r"))   (clobber (match_dup 0))   (clobber (match_dup 1))]  ""  "* return output_block_move (operands);");; Floating point move insns;; This pattern forces (set (reg:DF ...) (const_double ...));; to be reloaded by putting the constant into memory.;; It must come before the more general movdf pattern.(define_insn ""  [(set (match_operand:DF 0 "general_operand" "=r,f,o")	(match_operand:DF 1 "" "mG,m,G"))]  "GET_CODE (operands[1]) == CONST_DOUBLE"  "*{  if (FP_REG_P (operands[0]))    return output_fp_move_double (operands);  if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == REG)    {      operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);      return \"mov r0,%0\;mov r0,%1\";    }  if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == MEM)    {      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))	{	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)		 && (cc_prev_status.flags & CC_HI_R31_ADJ)		 && XEXP (operands[0], 0) == cc_prev_status.mdep))	    {	      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;	      cc_status.mdep = XEXP (operands[0], 0);	      output_asm_insn (\"orh ha%%%m0,r0,r31\", operands);	    }	  return \"st.l r0,l%%%m0(r31)\;st.l r0,l%%%m0+4(r31)\";	}      operands[1] = adj_offsettable_operand (operands[0], 4);      return \"st.l r0,%0\;st.l r0,%1\";    }  return output_move_double (operands);}")(define_insn "movdf"  [(set (match_operand:DF 0 "general_operand" "=*rm,&*r,?f,?*rm")	(match_operand:DF 1 "general_operand" "*r,m,*rfmG,f"))]  ""  "*{  if (GET_CODE (operands[0]) == MEM      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))    return output_store (operands);  if (GET_CODE (operands[1]) == MEM      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))    return output_load (operands);  /* Note that the only CONST_DOUBLE that should be possible is 0.  */  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])      || GET_CODE (operands[1]) == CONST_DOUBLE)    return output_fp_move_double (operands);  return output_move_double (operands);}")(define_insn "movdi"  [(set (match_operand:DI 0 "general_operand" "=rm,&r,?f,?rm")	(match_operand:DI 1 "general_operand" "r,miF,rfmG,fG"))]  ""  "*{  if (GET_CODE (operands[0]) == MEM      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))    return output_store (operands);  if (GET_CODE (operands[1]) == MEM      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))    return output_load (operands);  if (FP_REG_P (operands[0]) && operands[1] == dconst0_rtx)    return \"fmov.dd f0,%0\";  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))    return output_fp_move_double (operands);  return output_move_double (operands);}");; The alternative m/r is separate from m/f;; so that an f-reg won't be used as a reload reg between m and F.;; The first alternative is separate from the second for the same reason.(define_insn "movsf"  [(set (match_operand:SF 0 "general_operand" "=*rf,*rf,*r,m,m")	(match_operand:SF 1 "general_operand" "*r,fmG,F,*r,fG"))]  ""  "*{  if (GET_CODE (operands[0]) == MEM      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))    return output_store (operands);  if (GET_CODE (operands[1]) == MEM      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))    return output_load (operands);  if (FP_REG_P (operands[0]))    {      if (FP_REG_P (operands[1]))	return \"fmov.ss %1,%0\";      if (GET_CODE (operands[1]) == REG)	return \"ixfr %1,%0\";      if (operands[1] == fconst0_rtx)        return \"fmov.ss f0,%0\";