if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))	{	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)		 && (cc_prev_status.flags & CC_HI_R31_ADJ)		 && cc_prev_status.mdep == XEXP(operands[1],0)))	    output_asm_insn(\"orh ha%%%m1,r0,r31\",operands);	  cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;	  cc_status.mdep = XEXP (operands[1], 0);	  return \"fld.l l%%%m1(r31),%0\";	}      return \"fld.l %1,%0\";    }  if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)    {      if (GET_CODE (operands[0]) == REG && FP_REG_P (operands[1]))	return \"fxfr %1,%0\";      if (GET_CODE (operands[0]) == REG)        return \"mov %1,%0\";      /* Now operand 0 must be memory.         If operand 1 is CONST_DOUBLE, its value must be 0.  */      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))	{	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)		 && (cc_prev_status.flags & CC_HI_R31_ADJ)		 && XEXP (operands[0], 0) == cc_prev_status.mdep))	    {	      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;	      cc_status.mdep = XEXP (operands[0], 0);	      output_asm_insn (\"orh ha%%%m0,r0,r31\", operands);	    }	  return \"fst.l %r1,l%%%m0(r31)\";	}      return \"fst.l %r1,%0\";    }  if (GET_CODE (operands[0]) == MEM)    return \"st.l %r1,%0\";  if (GET_CODE (operands[1]) == MEM)    return \"ld.l %1,%0\";  if (operands[1] == fconst0_rtx)    return \"mov r0,%0\";  return \"mov %1,%0\";}");; Special load insns for REG+REG addresses.;; Such addresses are not "legitimate" because st rejects them.(define_insn ""  [(set (match_operand:DF 0 "register_operand" "=rf")	(match_operand:DF 1 "indexed_operand" "m"))]  ""  "*{  if (FP_REG_P (operands[0]))    return output_fp_move_double (operands);  return output_move_double (operands);}")(define_insn ""  [(set (match_operand:SF 0 "register_operand" "=rf")	(match_operand:SF 1 "indexed_operand" "m"))]  ""  "*{  if (FP_REG_P (operands[0]))    return \"fld.l %1,%0\";  return \"ld.l %1,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=rf")	(match_operand:SI 1 "indexed_operand" "m"))]  ""  "*{  if (FP_REG_P (operands[0]))    return \"fld.l %1,%0\";  return \"ld.l %1,%0\";}")(define_insn ""  [(set (match_operand:HI 0 "register_operand" "=r")	(match_operand:HI 1 "indexed_operand" "m"))]  ""  "ld.s %1,%0")(define_insn ""  [(set (match_operand:QI 0 "register_operand" "=r")	(match_operand:QI 1 "indexed_operand" "m"))]  ""  "ld.b %1,%0");; Likewise for floating-point store insns.(define_insn ""  [(set (match_operand:DF 0 "indexed_operand" "=m")	(match_operand:DF 1 "register_operand" "f"))]  ""  "fst.d %1,%0")(define_insn ""  [(set (match_operand:SF 0 "indexed_operand" "=m")	(match_operand:SF 1 "register_operand" "f"))]  ""  "fst.l %1,%0");;- truncation instructions(define_insn "truncsiqi2"  [(set (match_operand:QI 0 "general_operand" "=g")	(truncate:QI	 (match_operand:SI 1 "register_operand" "r")))]  ""  "*{  if (GET_CODE (operands[0]) == MEM)    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))      {	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)	       && (cc_prev_status.flags & CC_HI_R31_ADJ)	       && XEXP (operands[0], 0) == cc_prev_status.mdep))	  {	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;	    cc_status.mdep = XEXP (operands[0], 0);	    output_asm_insn (\"orh ha%%%m0,r0,r31\", operands);	  }	return \"st.b %1,l%%%m0(r31)\";      }    else      return \"st.b %1,%0\";  return \"mov %1,%0\";}")(define_insn "trunchiqi2"  [(set (match_operand:QI 0 "general_operand" "=g")	(truncate:QI	 (match_operand:HI 1 "register_operand" "r")))]  ""  "*{  if (GET_CODE (operands[0]) == MEM)    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))      {	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)	       && (cc_prev_status.flags & CC_HI_R31_ADJ)	       && XEXP (operands[0], 0) == cc_prev_status.mdep))	  {	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;	    cc_status.mdep = XEXP (operands[0], 0);	    output_asm_insn (\"orh ha%%%m0,r0,r31\", operands);	  }	return \"st.b %1,l%%%m0(r31)\";      }    else      return \"st.b %1,%0\";  return \"mov %1,%0\";}")(define_insn "truncsihi2"  [(set (match_operand:HI 0 "general_operand" "=g")	(truncate:HI	 (match_operand:SI 1 "register_operand" "r")))]  ""  "*{  if (GET_CODE (operands[0]) == MEM)    if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))      {	if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)	       && (cc_prev_status.flags & CC_HI_R31_ADJ)	       && XEXP (operands[0], 0) == cc_prev_status.mdep))	  {	    cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;	    cc_status.mdep = XEXP (operands[0], 0);	    output_asm_insn (\"orh ha%%%m0,r0,r31\", operands);	  }	return \"st.s %1,l%%%m0(r31)\";      }    else      return \"st.s %1,%0\";  return \"mov %1,%0\";}");;- zero extension instructions;; Note that the one starting from HImode comes before those for QImode;; so that a constant operand will match HImode, not QImode.(define_insn "zero_extendhisi2"  [(set (match_operand:SI 0 "register_operand" "=r")	(zero_extend:SI	 (match_operand:HI 1 "register_operand" "r")))]  ""  "and 0xffff,%1,%0")(define_insn "zero_extendqihi2"  [(set (match_operand:HI 0 "register_operand" "=r")	(zero_extend:HI	 (match_operand:QI 1 "register_operand" "r")))]  ""  "and 0xff,%1,%0")(define_insn "zero_extendqisi2"  [(set (match_operand:SI 0 "register_operand" "=r")	(zero_extend:SI	 (match_operand:QI 1 "register_operand" "r")))]  ""  "and 0xff,%1,%0");;- sign extension instructions;; Note that the one starting from HImode comes before those for QImode;; so that a constant operand will match HImode, not QImode.(define_insn "extendhisi2"  [(set (match_operand:SI 0 "register_operand" "=r")	(sign_extend:SI	 (match_operand:HI 1 "general_operand" "mr")))]  ""  "*{  if (REG_P (operands[1]))    return \"shl 16,%1,%0\;shra 16,%0,%0\";  if (GET_CODE (operands[1]) == CONST_INT)    abort ();  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))    {      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;      cc_status.mdep = XEXP (operands[1], 0);      return \"orh ha%%%m1,r0,r31\;ld.s l%%%m1(r31),%0\";    }  else    return \"ld.s %1,%0\";}")(define_insn "extendqihi2"  [(set (match_operand:HI 0 "register_operand" "=r")	(sign_extend:HI	 (match_operand:QI 1 "general_operand" "mr")))]  ""  "*{  if (REG_P (operands[1]))    return \"shl 24,%1,%0\;shra 24,%0,%0\";  if (GET_CODE (operands[1]) == CONST_INT)    abort ();  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))    {      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;      cc_status.mdep = XEXP (operands[1], 0);      return \"orh ha%%%m1,r0,r31\;ld.b l%%%m1(r31),%0\";    }  else    return \"ld.b %1,%0\";}")(define_insn "extendqisi2"  [(set (match_operand:SI 0 "register_operand" "=r")	(sign_extend:SI	 (match_operand:QI 1 "general_operand" "mr")))]  ""  "*{  if (REG_P (operands[1]))    return \"shl 24,%1,%0\;shra 24,%0,%0\";  if (GET_CODE (operands[1]) == CONST_INT)    abort ();  if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))    {      cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;      cc_status.mdep = XEXP (operands[1], 0);      return \"orh ha%%%m1,r0,r31\;ld.b l%%%m1(r31),%0\";    }  else    return \"ld.b %1,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(sign_extend:SI	 (match_operand:HI 1 "indexed_operand" "m")))]  ""  "ld.s %1,%0")(define_insn ""  [(set (match_operand:HI 0 "register_operand" "=r")	(sign_extend:HI	 (match_operand:QI 1 "indexed_operand" "m")))]  ""  "ld.b %1,%0")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(sign_extend:SI	 (match_operand:QI 1 "indexed_operand" "m")))]  ""  "ld.b %1,%0");; Signed bitfield extractions come out looking like;;	(shiftrt (sign_extend (shift <Y> <C1>)) <C2>);; which we expand poorly as four shift insns.;; These patters yeild two shifts:;;	(shiftrt (shift <Y> <C3>) <C4>)(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(ashiftrt:SI	 (sign_extend:SI	  (match_operand:QI 1 "register_operand" "r"))	 (match_operand:SI 2 "logic_int" "n")))]  "INTVAL (operands[2]) < 8"  "*{  return \"shl 24,%1,%0\;shra 24+%2,%0,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(ashiftrt:SI	 (sign_extend:SI	  (subreg:QI (ashift:SI (match_operand:SI 1 "register_operand" "r")				(match_operand:SI 2 "logic_int" "n")) 0))	 (match_operand:SI 3 "logic_int" "n")))]  "INTVAL (operands[3]) < 8"  "*{  return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "register_operand" "=r")	(ashiftrt:SI	 (sign_extend:SI	  (ashift:QI (match_operand:QI 1 "register_operand" "r")		     (match_operand:QI 2 "logic_int" "n")))	 (match_operand:SI 3 "logic_int" "n")))]  "INTVAL (operands[3]) < 8"  "*{  return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";}");; Special patterns for optimizing bit-field instructions.;; First two patterns are for bitfields that came from memory;; testing only the high bit.  They work with old combiner.(define_insn ""  [(set (cc0)	(eq (zero_extend:SI (subreg:QI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r")						    (const_int 7)) 0))	    (const_int 0)))]  ""  "and 128,%0,r0")(define_insn ""  [(set (cc0)	(eq (sign_extend:SI (subreg:QI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r")						    (const_int 7)) 0))	    (const_int 0)))]  ""  "and 128,%0,r0");; next two patterns are good for bitfields coming from memory;; (via pseudo-register) or from a register, though this optimization;; is only good for values contained wholly within the bottom 16 bits(define_insn ""  [(set (cc0)	(eq 	 (and:SI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r")			      (match_operand:SI 1 "logic_int" "n"))		 (match_operand:SI 2 "logic_int" "n"))	 (const_int 0)))]  "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))"  "*{  operands[2] = gen_rtx (CONST_INT, VOIDmode,			 (INTVAL (operands[2]) << INTVAL (operands[1])));  return \"and %2,%0,r0\";}")(define_insn ""  [(set (cc0)	(eq 	 (and:SI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r")			      (match_operand:SI 1 "logic_int" "n"))		 (match_operand:SI 2 "logic_int" "n"))	 (const_int 0)))]  "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))"  "*{  operands[2] = gen_rtx (CONST_INT, VOIDmode,			 (INTVAL (operands[2]) << INTVAL (operands[1])));  return \"and %2,%0,r0\";}");; Conversions between float and double.(define_insn "extendsfdf2"  [(set (match_operand:DF 0 "register_operand" "=f")	(float_extend:DF	 (match_operand:SF 1 "register_operand" "f")))]  ""  "fmov.sd %1,%0")(define_insn "truncdfsf2"  [(set (match_operand:SF 0 "register_operand" "=f")	(float_truncate:SF	 (match_operand:DF 1 "register_operand" "f")))]  ""  "fmov.ds %1,%0");; Conversion between fixed point and floating point.;; Note that among the fix-to-float insns;; the ones that start with SImode come first.;; That is so that an operand that is a CONST_INT;; (and therefore lacks a specific machine mode).;; will be recognized as SImode (which is always valid);; rather than as QImode or HImode.(define_expand "floatsidf2"  [(set (match_dup 2) (match_dup 3))   (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "")			      (const_int -2147483648)))   (set (subreg:SI (match_dup 5) 0) (match_dup 4))   (set (subreg:SI (match_dup 5) 1) (subreg:SI (match_dup 2) 1))   (set (match_operand:DF 0 "register_operand" "")	(minus:DF (match_dup 5) (match_dup 2)))]  ""  "{  /* Generate desired value, in float format of host machine.  */  double d = (double) (1 << 30) * ((double) (1 << 22) + (double) (1 << 1));  operands[2] = gen_reg_rtx (DFmode);  operands[3] = immed_double_const (d, DFmode);  operands[4] = gen_reg_rtx (SImode);  operands[5] = gen_reg_rtx (DFmode);}");; Floating to fixed conversion.(define_expand "fix_truncdfsi2"  ;; This first insn produces a double-word value  ;; in which only the low word is valid.  [(set (match_dup 2)	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))   (set (match_operand:SI 0 "register_operand" "=f")	(subreg:SI (match_dup 2) 0))]  ""  "{  operands[2] = gen_reg_rtx (DImode);}");; Recognize the first insn generated above.;; This RTL looks like a fix_truncdfdi2 insn,;; but we dont call it that, because only 32 bits;; of the result are valid.;; This pattern will work for the intended purposes ;; as long as we do not have any fixdfdi2 or fix_truncdfdi2.(define_insn ""  [(set (match_operand:DI 0 "register_operand" "=f")	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]  ""  "ftrunc.dd %1,%0")(define_expand "fix_truncsfsi2"  ;; This first insn produces a double-word value  ;; in which only the low word is valid.  [(set (match_dup 2)	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))   (set (match_operand:SI 0 "register_operand" "=f")	(subreg:SI (match_dup 2) 0))]  ""  "{  operands[2] = gen_reg_rtx (DImode);}");; Recognize the first insn generated above.;; This RTL looks like a fix_truncsfdi2 insn,;; but we dont call it that, because only 32 bits;; of the result are valid.;; This pattern will work for the intended purposes ;; as long as we do not have any fixsfdi2 or fix_truncsfdi2.(define_insn ""  [(set (match_operand:DI 0 "register_operand" "=f")	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]  ""  "ftrunc.sd %1,%0");;- arithmetic instructions(define_insn "addsi3"  [(set (match_operand:SI 0 "register_operand" "=r,*f")	(plus:SI (match_operand:SI 1 "nonmemory_operand" "%r,*f")		 (match_operand:SI 2 "nonmemory_operand" "rn,*f")))]  ""  "*{  if (which_alternative == 1)    return \"fiadd.ss %2,%1,%0\";  if (REG_P (operands[2]))    return \"addu %2,%1,%0\";  if (SMALL_INT (operands[2]))    return \"addu %2,%1,%0\";  cc_status.flags &= ~CC_KNOW_HI_R31;  return \"orh h%%%2,r0,r31\;or l%%%2,r31,r31\;addu %1,r31,%0\";}")(define_insn "adddi3"  [(set (match_operand:DI 0 "register_operand" "=f")	(plus:DI (match_operand:DI 1 "register_operand" "%f")		 (match_operand:DI 2 "register_operand" "f")))]  ""  "fiadd.dd %1,%2,%0")(define_insn "subsi3"