;; Machine description for Pyramid 90 Series for GNU C compiler;; Copyright (C) 1989 Free Software Foundation, Inc.;; This file is part of GNU CC.;; GNU CC is free software; you can redistribute it and/or modify;; it under the terms of the GNU General Public License as published by;; the Free Software Foundation; either version 1, or (at your option);; any later version.;; GNU CC is distributed in the hope that it will be useful,;; but WITHOUT ANY WARRANTY; without even the implied warranty of;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the;; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License;; along with GNU CC; see the file COPYING.  If not, write to;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.;; Instruction patterns.  When multiple patterns apply,;; the first one in the file is chosen.;;;; See file "rtl.def" for documentation on define_insn, match_*, et. al.;;;; cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code;; updates for most instructions.;; * Try using define_insn instead of some peepholes in more places.;; * Set REG_NOTES:REG_EQUIV for cvt[bh]w loads.  This would make the;;   backward scan in sign_extend needless.;; * Match (pc) (label_ref) case in peephole patterns.;; * Should optimize;;   "cmpX op1,op2;  b{eq,ne} LY;  ucmpX op1.op2;  b{lt,le,gt,ge} LZ";;   to;;   "ucmpX op1,op2;  b{eq,ne} LY;  b{lt,le,gt,ge} LZ";;   by pre-scanning insn and running notice_update_cc for them.;; * Is it necessary to do copy_rtx in the test and compare patterns?;; * Fix true frame pointer omission.;; * Make the jump tables contain branches, not addresses!  This would;;   save us one instruction.;; * Could the compilcated scheme for compares be simplyfied, if we had;;   no named cmpqi or cmphi patterns, and instead anonymous patterns for;;   the less-than-word compare cases pyr can handle???;; * The jump insn seems to accept more than just IR addressing.  Would;;   we win by telling GCC?  Or can we use movw into the global reg which;;   is a synonym for pc?;; * More DImode patterns.;; * Scan backwards in "zero_extendhisi2", "zero_extendqisi2" to find out;;   if the extension can be omitted.;; * "divmodsi" with Pyramid "ediv" insn.  Is it possible in rtl??;; * Would "rcsp tmpreg; u?cmp[bh] op1_regdispl(tmpreg),op2" win in;;   comparison with the two extensions and single test generated now?;;   The rcsp insn could be expanded, and moved out of loops by the;;   optimizer, making 1 (64 bit) insn of 3 (32 bit) insns in loops.;;   The rcsp insn could be followed by an add insn, making non-displacement;;   IR addressing sufficient.;______________________________________________________________________;;	Test and Compare Patterns.;______________________________________________________________________; The argument for the rather complicated test and compare expansion; scheme, is the irregular pyramid instructions for these operations.; 1) Pyramid has different signed and unsigned compares.  2) HImode; and QImode integers are memory-memory and immediate-memory only.  3); Unsigned HImode compares doesn't exist.  4) Only certain; combinations of addresses are allowed for memory-memory compares.; Whenever necessary, in order to fulfill these addressing; constraints, the compare operands are swapped.(define_expand "tstsi"  [(set (cc0)	(match_operand:SI 0 "general_operand" ""))]  "" "operands[0] = force_reg (SImode, operands[0]);")(define_insn ""  [(set (cc0)	(compare (match_operand:SI 0 "memory_operand" "m")		 (match_operand:SI 1 "memory_operand" "m")))]  "weird_memory_memory (operands[0], operands[1])"  "*{  rtx br_insn = NEXT_INSN (insn);  RTX_CODE br_code;  if (GET_CODE (br_insn) != JUMP_INSN)    abort();  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));  weird_memory_memory (operands[0], operands[1]);  if (swap_operands)    {      cc_status.flags = CC_REVERSED;      if (TRULY_UNSIGNED_COMPARE_P (br_code))	{	  cc_status.mdep = CC_VALID_FOR_UNSIGNED;	  return \"ucmpw %0,%1\";	}      return \"cmpw %0,%1\";    }  if (TRULY_UNSIGNED_COMPARE_P (br_code))    {      cc_status.mdep = CC_VALID_FOR_UNSIGNED;      return \"ucmpw %1,%0\";    }  return \"cmpw %1,%0\";}")(define_insn "cmpsi"  [(set (cc0)	(compare (match_operand:SI 0 "general_operand" "r,g")		 (match_operand:SI 1 "general_operand" "g,r")))]  ""  "*{  rtx br_insn = NEXT_INSN (insn);  RTX_CODE br_code;  if (GET_CODE (br_insn) != JUMP_INSN)    abort();  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));  if (which_alternative != 0)    {      cc_status.flags = CC_REVERSED;      if (TRULY_UNSIGNED_COMPARE_P (br_code))	{	  cc_status.mdep = CC_VALID_FOR_UNSIGNED;	  return \"ucmpw %0,%1\";	}      return \"cmpw %0,%1\";    }  if (TRULY_UNSIGNED_COMPARE_P (br_code))    {      cc_status.mdep = CC_VALID_FOR_UNSIGNED;      return \"ucmpw %1,%0\";    }  return \"cmpw %1,%0\";}")(define_insn ""  [(set (cc0)	(match_operand:SI 0 "general_operand" "r"))]  ""  "*{  rtx br_insn = NEXT_INSN (insn);  RTX_CODE br_code;  if (GET_CODE (br_insn) != JUMP_INSN)    abort();  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));  if (TRULY_UNSIGNED_COMPARE_P (br_code))    {      cc_status.mdep = CC_VALID_FOR_UNSIGNED;      return \"ucmpw $0,%0\";    }  return \"mtstw %0,%0\";}")(define_expand "cmphi"  [(set (cc0)	(compare (match_operand:HI 0 "general_operand" "")		 (match_operand:HI 1 "general_operand" "")))]  ""  "{  extern rtx test_op0, test_op1;  extern enum machine_mode test_mode;  test_op0 = copy_rtx (operands[0]);  test_op1 = copy_rtx (operands[1]);  test_mode = HImode;  DONE;}")(define_insn "tsthi"  [(set (cc0)	(match_operand:HI 0 "nonimmediate_operand" "rm"))]  ""  "*{  cc_status.flags = CC_NO_OVERFLOW;  return \"cvthw %0,lr15\";}")(define_insn ""  [(set (cc0)	(compare (match_operand:HI 0 "memory_operand" "m")		 (match_operand:HI 1 "memory_operand" "m")))]  "weird_memory_memory (operands[0], operands[1])"  "*{  rtx br_insn = NEXT_INSN (insn);  if (GET_CODE (br_insn) != JUMP_INSN)    abort();  weird_memory_memory (operands[0], operands[1]);  if (swap_operands)    {      cc_status.flags = CC_REVERSED;      return \"cmph %0,%1\";    }  return \"cmph %1,%0\";}")(define_insn ""  [(set (cc0)	(compare (match_operand:HI 0 "nonimmediate_operand" "r,m")		 (match_operand:HI 1 "nonimmediate_operand" "m,r")))]  "(GET_CODE (operands[0]) != GET_CODE (operands[1]))"  "*{  rtx br_insn = NEXT_INSN (insn);  if (GET_CODE (br_insn) != JUMP_INSN)    abort();  if (which_alternative != 0)    {      cc_status.flags = CC_REVERSED;      return \"cmph %0,%1\";    }  return \"cmph %1,%0\";}")(define_expand "cmpqi"  [(set (cc0)	(compare (match_operand:QI 0 "general_operand" "")		 (match_operand:QI 1 "general_operand" "")))]  ""  "{  extern rtx test_op0, test_op1;  extern enum machine_mode test_mode;  test_op0 = copy_rtx (operands[0]);  test_op1 = copy_rtx (operands[1]);  test_mode = QImode;  DONE;}")(define_insn "tstqi"  [(set (cc0)	(match_operand:QI 0 "nonimmediate_operand" "rm"))]  ""  "*{  cc_status.flags = CC_NO_OVERFLOW;  return \"cvtbw %0,lr15\";}")(define_insn ""  [(set (cc0)	(compare (match_operand:QI 0 "memory_operand" "m")		 (match_operand:QI 1 "memory_operand" "m")))]  "weird_memory_memory (operands[0], operands[1])"  "*{  rtx br_insn = NEXT_INSN (insn);  RTX_CODE br_code;  if (GET_CODE (br_insn) != JUMP_INSN)    abort();  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));  weird_memory_memory (operands[0], operands[1]);  if (swap_operands)    {      cc_status.flags = CC_REVERSED;      if (TRULY_UNSIGNED_COMPARE_P (br_code))	{	  cc_status.mdep = CC_VALID_FOR_UNSIGNED;	  return \"ucmpb %0,%1\";	}      return \"cmpb %0,%1\";    }  if (TRULY_UNSIGNED_COMPARE_P (br_code))    {      cc_status.mdep = CC_VALID_FOR_UNSIGNED;      return \"ucmpb %1,%0\";    }  return \"cmpb %1,%0\";}")(define_insn ""  [(set (cc0)	(compare (match_operand:QI 0 "nonimmediate_operand" "r,m")		 (match_operand:QI 1 "nonimmediate_operand" "m,r")))]  "(GET_CODE (operands[0]) != GET_CODE (operands[1]))"  "*{  rtx br_insn = NEXT_INSN (insn);  RTX_CODE br_code;  if (GET_CODE (br_insn) != JUMP_INSN)    abort();  br_code =  GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));  if (which_alternative != 0)    {      cc_status.flags = CC_REVERSED;      if (TRULY_UNSIGNED_COMPARE_P (br_code))	{	  cc_status.mdep = CC_VALID_FOR_UNSIGNED;	  return \"ucmpb %0,%1\";	}      return \"cmpb %0,%1\";    }  if (TRULY_UNSIGNED_COMPARE_P (br_code))    {      cc_status.mdep = CC_VALID_FOR_UNSIGNED;      return \"ucmpb %1,%0\";    }  return \"cmpb %1,%0\";}")(define_expand "bgt"  [(set (pc) (if_then_else (gt (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (SIGN_EXTEND);")(define_expand "blt"  [(set (pc) (if_then_else (lt (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (SIGN_EXTEND);")(define_expand "bge"  [(set (pc) (if_then_else (ge (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (SIGN_EXTEND);")(define_expand "ble"  [(set (pc) (if_then_else (le (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (SIGN_EXTEND);")(define_expand "beq"  [(set (pc) (if_then_else (eq (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (SIGN_EXTEND);")(define_expand "bne"  [(set (pc) (if_then_else (ne (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (SIGN_EXTEND);")(define_expand "bgtu"  [(set (pc) (if_then_else (gtu (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (ZERO_EXTEND);")(define_expand "bltu"  [(set (pc) (if_then_else (ltu (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (ZERO_EXTEND);")(define_expand "bgeu"  [(set (pc) (if_then_else (geu (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (ZERO_EXTEND);")(define_expand "bleu"  [(set (pc) (if_then_else (leu (cc0) (const_int 0))			   (label_ref (match_operand 0 "" "")) (pc)))]  "" "extend_and_branch (ZERO_EXTEND);")(define_insn "cmpdf"  [(set (cc0)	(compare (match_operand:DF 0 "register_operand" "r")		 (match_operand:DF 1 "register_operand" "r")))]  ""  "cmpd %1,%0")(define_insn "cmpsf"  [(set (cc0)	(compare (match_operand:SF 0 "register_operand" "r")		 (match_operand:SF 1 "register_operand" "r")))]  ""  "cmpf %1,%0")(define_insn "tstdf"  [(set (cc0)       	(match_operand:DF 0 "register_operand" "r"))]  ""  "mtstd %0,%0")(define_insn "tstsf"  [(set (cc0)       	(match_operand:SF 0 "register_operand" "r"))]  ""  "mtstf %0,%0");______________________________________________________________________;;	Fixed-point Arithmetic.;______________________________________________________________________(define_insn "addsi3"  [(set (match_operand:SI 0 "register_operand" "=r,!r")	(plus:SI (match_operand:SI 1 "general_operand" "%0,r")		 (match_operand:SI 2 "general_operand" "g,rJ")))]  ""  "*{  if (which_alternative == 0)    return \"addw %2,%0\";  else    {      forget_cc_if_dependent (operands[0]);      return REG_P (operands[2])	? \"mova (%2)[%1*1],%0\" : \"mova %a2[%1*1],%0\";    }}")(define_insn "subsi3"  [(set (match_operand:SI 0 "register_operand" "=r,r")	(minus:SI (match_operand:SI 1 "general_operand" "0,g")		  (match_operand:SI 2 "general_operand" "g,0")))]  ""  "* return (which_alternative == 0) ? \"subw %2,%0\" : \"rsubw %1,%0\";")(define_insn "mulsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(mult:SI (match_operand:SI 1 "general_operand" "%0")		 (match_operand:SI 2 "general_operand" "g")))]  ""  "mulw %2,%0")(define_insn "umulsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(umult:SI (match_operand:SI 1 "general_operand" "%0")		  (match_operand:SI 2 "general_operand" "g")))]  ""  "umulw %2,%0")(define_insn "divsi3"  [(set (match_operand:SI 0 "register_operand" "=r,r")	(div:SI (match_operand:SI 1 "general_operand" "0,g")		(match_operand:SI 2 "general_operand" "g,0")))]  ""  "* return (which_alternative == 0) ? \"divw %2,%0\" : \"rdivw %1,%0\";")(define_insn "udivsi3"  [(set (match_operand:SI 0 "register_operand" "=r")	(udiv:SI (match_operand:SI 1 "register_operand" "0")		 (match_operand:SI 2 "general_operand" "g")))]  ""  "udivw %2,%0")(define_insn "modsi3"  [(set (match_operand:SI 0 "register_operand" "=r")