-- Node name is '|DDS:13|:20' = '|DDS:13|REGIS5' 
-- Equation name is '_LC7_E14', type is buried 
_LC7_E14 = DFFE( _EQ017, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ017 =  _LC7_E14 &  START &  X
         # !_LC6_E14 &  _LC7_E14 &  START
         #  _LC6_E14 & !_LC7_E14 &  START & !X;

-- Node name is '|DDS:13|:19' = '|DDS:13|REGIS6' 
-- Equation name is '_LC5_E14', type is buried 
_LC5_E14 = DFFE( _EQ018, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ018 = !_LC2_E14 &  _LC5_E14 &  START & !X
         #  _LC2_E14 & !_LC5_E14 &  START
         # !_LC5_E14 &  START &  X;

-- Node name is '|DDS:13|:18' = '|DDS:13|REGIS7' 
-- Equation name is '_LC1_E14', type is buried 
_LC1_E14 = DFFE( _EQ019, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ019 =  _LC8_E14 &  START;

-- Node name is '|DDS:13|:17' = '|DDS:13|REGIS8' 
-- Equation name is '_LC2_E17', type is buried 
_LC2_E17 = DFFE( _EQ020, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ020 =  _LC6_E17 &  START;

-- Node name is '|DDS:13|:16' = '|DDS:13|REGIS9' 
-- Equation name is '_LC1_E5', type is buried 
_LC1_E5  = DFFE( _EQ021, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ021 =  _LC8_E5 &  START;

-- Node name is '|DDS:13|:15' = '|DDS:13|REGIS10' 
-- Equation name is '_LC3_E5', type is buried 
_LC3_E5  = DFFE( _EQ022, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ022 =  _LC6_E5 &  START;

-- Node name is '|DDS:13|:14' = '|DDS:13|REGIS11' 
-- Equation name is '_LC8_E17', type is buried 
_LC8_E17 = DFFE( _EQ023, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ023 =  _LC4_E1 &  START;

-- Node name is '|DDS:13|:13' = '|DDS:13|REGIS12' 
-- Equation name is '_LC2_E1', type is buried 
_LC2_E1  = DFFE( _EQ024, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ024 =  _LC8_E1 &  START;

-- Node name is '|DDS:13|:12' = '|DDS:13|REGIS13' 
-- Equation name is '_LC1_E1', type is buried 
_LC1_E1  = DFFE( _EQ025, GLOBAL( FCLK),  VCC,  VCC,  VCC);
  _EQ025 =  _LC5_E1 &  START & !X
         #  _LC7_E1 &  START &  X;

-- Node name is '|DDS:13|:301' 
-- Equation name is '_LC8_E1', type is buried 
_LC8_E1  = LCELL( _EQ026);
  _EQ026 =  _LC2_E1 & !_LC3_E1 & !X
         # !_LC2_E1 &  _LC3_E1 & !X
         #  _LC2_E1 & !_LC6_E1 &  X
         # !_LC2_E1 &  _LC6_E1 &  X;

-- Node name is '|DDS:13|:313' 
-- Equation name is '_LC4_E1', type is buried 
_LC4_E1  = LCELL( _EQ027);
  _EQ027 = !_LC2_E5 &  _LC8_E17 & !X
         #  _LC2_E5 & !_LC8_E17 & !X
         # !_LC1_E17 &  _LC8_E17 &  X
         #  _LC1_E17 & !_LC8_E17 &  X;

-- Node name is '|DDS:13|:325' 
-- Equation name is '_LC6_E5', type is buried 
_LC6_E5  = LCELL( _EQ028);
  _EQ028 =  _LC3_E5 & !_LC5_E5 & !X
         # !_LC3_E5 &  _LC5_E5 & !X
         #  _LC3_E5 & !_LC3_E17 &  X
         # !_LC3_E5 &  _LC3_E17 &  X;

-- Node name is '|DDS:13|:337' 
-- Equation name is '_LC8_E5', type is buried 
_LC8_E5  = LCELL( _EQ029);
  _EQ029 =  _LC1_E5 & !_LC4_E5 & !X
         # !_LC1_E5 &  _LC4_E5 & !X
         #  _LC1_E5 & !_LC7_E5 &  X
         # !_LC1_E5 &  _LC7_E5 &  X;

-- Node name is '|DDS:13|:349' 
-- Equation name is '_LC6_E17', type is buried 
_LC6_E17 = LCELL( _EQ030);
  _EQ030 =  _LC2_E17 & !_LC4_E17 & !X
         # !_LC2_E17 &  _LC4_E17 & !X
         #  _LC2_E17 & !_LC5_E17 &  X
         # !_LC2_E17 &  _LC5_E17 &  X;

-- Node name is '|DDS:13|:361' 
-- Equation name is '_LC8_E14', type is buried 
_LC8_E14 = LCELL( _EQ031);
  _EQ031 =  _LC1_E14 & !_LC2_E14 & !X
         # !_LC1_E14 &  _LC2_E14 &  _LC5_E14
         # !_LC1_E14 &  _LC5_E14 &  X
         #  _LC1_E14 & !_LC5_E14;

-- Node name is '|LH:10|lpm_rom:lpm_rom_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_E', type is memory 
_EC3_E   = MEMORY_SEGMENT( VCC, GLOBAL( FCLK), VCC, GND, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LH:10|lpm_rom:lpm_rom_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_E', type is memory 
_EC10_E  = MEMORY_SEGMENT( VCC, GLOBAL( FCLK), VCC, GND, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LH:10|lpm_rom:lpm_rom_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_E', type is memory 
_EC2_E   = MEMORY_SEGMENT( VCC, GLOBAL( FCLK), VCC, GND, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LH:10|lpm_rom:lpm_rom_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC11_E', type is memory 
_EC11_E  = MEMORY_SEGMENT( VCC, GLOBAL( FCLK), VCC, GND, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LH:10|lpm_rom:lpm_rom_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_E', type is memory 
_EC1_E   = MEMORY_SEGMENT( VCC, GLOBAL( FCLK), VCC, GND, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LH:10|lpm_rom:lpm_rom_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_E', type is memory 
_EC9_E   = MEMORY_SEGMENT( VCC, GLOBAL( FCLK), VCC, GND, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LH:10|lpm_rom:lpm_rom_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_E', type is memory 
_EC4_E   = MEMORY_SEGMENT( VCC, GLOBAL( FCLK), VCC, GND, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LH:10|lpm_rom:lpm_rom_component|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC12_E', type is memory 
_EC12_E  = MEMORY_SEGMENT( VCC, GLOBAL( FCLK), VCC, GND, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, _LC5_E14, _LC1_E14, _LC2_E17, _LC1_E5, _LC3_E5, _LC8_E17, _LC2_E1, _LC1_E1, VCC, VCC, VCC, VCC, VCC, VCC);



Project Information                  e:\lsz\job\ksprogramme\13\dds\zhenghe.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,200K