LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
   PORT
    (CLK:IN STD_LOGIC;
	 X,START: in STD_LOGIC;
     ADDRESS: OUT STD_LOGIC_VECTOR(7 downto 0)    
    );
END DDS;

ARCHITECTURE BEHAVE OF DDS IS
signal REGIS : std_logic_vector(13 downto 0);
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
 IF START='0' THEN REGIS<="00000000000000";
 ELSIF X='1' THEN REGIS<=REGIS+"00000001000000";
 ELSIF X='0' THEN REGIS<=REGIS+"00000000001000";
 END IF;
END IF;
ADDRESS<=REGIS(13 DOWNTO 6);
END PROCESS;
END BEHAVE;