Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       d:\rest_1\cpld\statmach.rpt
statmach

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (34)    23    B       SOFT      t        0      0   0    0    2    1    0  |LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
 (38)    20    B       SOFT      t        0      0   0    0    4    1    0  |LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                       d:\rest_1\cpld\statmach.rpt
statmach

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                       Logic cells placed in LAB 'B'
        +------------- LC18 COUNT0
        | +----------- LC19 COUNT1
        | | +--------- LC21 COUNT2
        | | | +------- LC17 COUNT3
        | | | | +----- LC23 |LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
        | | | | | +--- LC20 |LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
        | | | | | | +- LC22 OV
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC18 -> * * * * * * * | - * | <-- COUNT0
LC19 -> - * * * * * * | - * | <-- COUNT1
LC21 -> - * * * - * * | - * | <-- COUNT2
LC17 -> - * - * - * * | - * | <-- COUNT3
LC23 -> - * - - - - - | - * | <-- |LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC20 -> - - - * - - - | - * | <-- |LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3

Pin
43   -> - - - - - - - | - - | <-- CP
4    -> * * * * - - * | - * | <-- RESET


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                       d:\rest_1\cpld\statmach.rpt
statmach

** EQUATIONS **

CP       : INPUT;
RESET    : INPUT;

-- Node name is 'COUNT0' = 'COUN0' 
-- Equation name is 'COUNT0', location is LC018, type is output.
 COUNT0  = TFFE( VCC, GLOBAL( CP), !RESET,  VCC,  VCC);

-- Node name is 'COUNT1' = 'COUN1' 
-- Equation name is 'COUNT1', location is LC019, type is output.
 COUNT1  = DFFE( _EQ001 $  _LC023, GLOBAL( CP), !RESET,  VCC,  VCC);
  _EQ001 =  COUNT0 & !COUNT1 & !COUNT2 &  COUNT3 &  _LC023;

-- Node name is 'COUNT2' = 'COUN2' 
-- Equation name is 'COUNT2', location is LC021, type is output.
 COUNT2  = TFFE( _EQ002, GLOBAL( CP), !RESET,  VCC,  VCC);
  _EQ002 =  COUNT0 &  COUNT1;

-- Node name is 'COUNT3' = 'COUN3' 
-- Equation name is 'COUNT3', location is LC017, type is output.
 COUNT3  = DFFE( _EQ003 $  _LC020, GLOBAL( CP), !RESET,  VCC,  VCC);
  _EQ003 =  COUNT0 & !COUNT1 & !COUNT2 &  COUNT3 &  _LC020;

-- Node name is 'OV' = ':3' 
-- Equation name is 'OV', type is output 
 OV      = DFFE( _EQ004 $  GND, GLOBAL( CP), !RESET,  VCC,  VCC);
  _EQ004 =  COUNT0 & !COUNT1 & !COUNT2 &  COUNT3;

-- Node name is '|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( COUNT1 $  COUNT0);

-- Node name is '|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( COUNT3 $  _EQ005);
  _EQ005 =  COUNT0 &  COUNT1 &  COUNT2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                d:\rest_1\cpld\statmach.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,525K