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-- LogiBLOX CLK_DIV Module "CLK_DIV"
-- Created by LogiBLOX version D.19
--    on Fri Nov 29 16:48:44 2002
-- Attributes 
--    MODTYPE = CLK_DIV
--    DIVIDE_BY = 256
--    DUTY_CYCLE = 240
--    ASYNC_COUNT = 16
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-- This is a behaviorial model only and cannot be synthesized.
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

-- synopsys translate_off
LIBRARY logiblox;
USE logiblox.mvlutil.ALL;
USE logiblox.mvlarith.ALL;
USE logiblox.logiblox.ALL;
-- synopsys translate_on

ENTITY CLK_DIV IS
  PORT(
    ASYNC_CTRL: IN std_logic;
    CLOCK: IN std_logic;
    CLK_OUT: OUT std_logic);
END CLK_DIV;

-- synopsys translate_off
ARCHITECTURE sim OF CLK_DIV IS
    SIGNAL START_PULSE: std_logic := '1';
BEGIN
  PROCESS
    VARIABLE VASYNC_CTRL: std_logic;
    VARIABLE VSYNC_CTRL: std_logic;
    VARIABLE VCLK_EN: std_logic;
    VARIABLE VCLOCK: std_logic;
    VARIABLE VCLK_OUT: std_logic;
    VARIABLE curr_cycle: INTEGER;
    BEGIN
      VASYNC_CTRL := stdbit2mvl(ASYNC_CTRL);
      VSYNC_CTRL := '0';
      IF(
       (CLOCK'EVENT AND stdbit2mvl(CLOCK)='1' AND stdbit2mvl(CLOCK'LAST_VALUE)='0')
       OR (ASYNC_CTRL'EVENT AND stdbit2mvl(ASYNC_CTRL) /= '0')
       OR ( stdbit2mvl(START_PULSE)='1')
      ) THEN
      xb_clk_div(START_PULSE, -- start_pulse
               VASYNC_CTRL,
               16, -- ASYNC_COUNT
               VSYNC_CTRL,
               0, -- SYNC_COUNT
               256, -- divide_by
               240, -- duty_cycle
               curr_cycle,
               VCLK_OUT);
      CLK_OUT <= VCLK_OUT;
      ELSIF(
       (stdbit2mvl(CLOCK) = 'X' AND stdbit2mvl(ASYNC_CTRL) /= '1')
      ) THEN
      VCLK_OUT := ('X');
      CLK_OUT <= VCLK_OUT;
      curr_cycle := -1;
      END IF;
      IF (START_PULSE='1') THEN
        START_PULSE <= '0' AFTER 1 ns;
      END IF;
      WAIT ON ASYNC_CTRL, CLOCK, START_PULSE;
  END PROCESS;
END sim;
-- synopsys translate_on