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Project Informatione:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
MAX+plus II Compiler Report File
Version 9.6 3/22/2000
Compiled: 08/08/2000 11:05:31
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir LCs
POF Device Pins Pins Pins LCs % Utilized
cc1 EPF8282ALC84-4 1 8 0 72 34 %
User Pins: 1 8 0
Project Informatione:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
cc1@12 clk
cc1@84 out0
cc1@83 out1
cc1@82 out2
cc1@81 out3
cc1@79 out4
cc1@78 out5
cc1@77 out6
cc1@76 out7
Project Informatione:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
** FILE HIERARCHY **
|lpm_add_sub:513|
|lpm_add_sub:513|addcore:adder|
|lpm_add_sub:513|altshift:result_ext_latency_ffs|
|lpm_add_sub:513|altshift:carry_ext_latency_ffs|
|lpm_add_sub:513|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:514|
|lpm_add_sub:514|addcore:adder|
|lpm_add_sub:514|altshift:result_ext_latency_ffs|
|lpm_add_sub:514|altshift:carry_ext_latency_ffs|
|lpm_add_sub:514|altshift:oflow_ext_latency_ffs|
Device-Specific Information:e:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
cc1
***** Logic for device 'cc1' compiled without errors.
Device: EPF8282ALC84-4
FLEX 8000 Configuration Scheme: Active Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable DCLK Output in User Mode = OFF
Disable Start-Up Time-Out = OFF
Enable JTAG Support = OFF
Device-Specific Information:e:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
cc1
** ERROR SUMMARY **
Info: Node 'out4' assigned to pin '79' will not be tri-stated during device configuration
^
C
O R R R R R R R R
N E E E E E E E E
F S S S S S S S S V
_ ^ E E E E E E E E C
D D R R R R R R R R o o o o C o o o o ^
O C V V V V G V V V V u u u u I u u u u n
N L E E E E N E E E E t t t t N t t t t S
E K D D D D D D D D D 0 1 2 3 T 4 5 6 7 P
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
clk | 12 74 | ^MSEL0
RESERVED | 13 73 | GND
+DATA0 | 14 72 | RESERVED
RESERVED | 15 71 | RESERVED
RESERVED | 16 70 | RESERVED
VCCINT | 17 69 | RESERVED
RESERVED | 18 68 | GND
RESERVED | 19 67 | RESERVED
RESERVED | 20 66 | RESERVED
RESERVED | 21 65 | RESERVED
RESERVED | 22 EPF8282ALC84-4 64 | RESERVED
RESERVED | 23 63 | RESERVED
RESERVED | 24 62 | RESERVED
RESERVED | 25 61 | RESERVED
GND | 26 60 | RESERVED
RESERVED | 27 59 | VCCINT
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | RESERVED
RESERVED | 30 56 | RESERVED
GND | 31 55 | RESERVED
^nSTATUS | 32 54 | GND
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
^ R R R R V R R R R R R R R G R R R R G ^
n E E E E C E E E E E E E E N E E E E N M
C S S S S C S S S S S S S S D S S S S D S
O E E E E I E E E E E E E E E E E E E
N R R R R N R R R R R R R R R R R R L
F V V V V T V V V V V V V V V V V V 1
I E E E E E E E E E E E E E E E E
G D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
cc1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 6/24( 25%)
A3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/24( 16%)
A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/24( 16%)
A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/24( 16%)
A8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/24( 16%)
A9 4/ 8( 50%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 8/24( 33%)
A10 5/ 8( 62%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 6/24( 25%)
A11 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 8/24( 33%)
A12 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/24( 12%)
A13 3/ 8( 37%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 6/24( 25%)
B2 6/ 8( 75%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 3/24( 12%)
B3 6/ 8( 75%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 3/24( 12%)
B4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 4/24( 16%)
B5 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 8/24( 33%)
B6 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 1/2 1/2 5/24( 20%)
B7 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 1/2 2/24( 8%)
B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/24( 8%)
B12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 1/2 2/24( 8%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 9/64 ( 14%)
Total logic cells used: 72/208 ( 34%)
Average fan-in: 3.27/4 ( 81%)
Total fan-in: 236/832 ( 28%)
Total input pins required: 1
Total input I/O cell registers required: 0
Total output pins required: 8
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 1
Total logic cells required: 72
Total flipflops required: 24
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Synthesized logic cells: 25/ 208 ( 12%)
Logic Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 Total
A: 8 0 1 0 0 1 1 1 4 5 8 2 3 34
B: 0 6 6 8 8 7 1 1 0 0 0 1 0 38
Total: 8 6 7 8 8 8 2 2 4 5 8 3 3 72
Device-Specific Information:e:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
cc1
** INPUTS **
Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
12 - - -- INPUT G 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
cc1
** OUTPUTS **
Fed By Fan-In Fan-Out
Pin LC Row Col Primitive Code INP FBK OUT FBK Name
84 - - 09 OUTPUT 0 1 0 0 out0
83 - - 09 OUTPUT 0 1 0 0 out1
82 - - 10 OUTPUT 0 1 0 0 out2
81 - - 11 OUTPUT 0 1 0 0 out3
79 - - 11 OUTPUT 0 1 0 0 out4
78 - - 12 OUTPUT 0 1 0 0 out5
77 - - 13 OUTPUT 0 1 0 0 out6
76 - - 13 OUTPUT 0 1 0 0 out7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:e:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt
cc1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- 6 A 01 AND2 0 2 0 1 |lpm_add_sub:513|addcore:adder|:55
- 4 B 04 AND2 0 2 0 3 |lpm_add_sub:514|addcore:adder|:119
- 3 B 04 AND2 0 3 0 3 |lpm_add_sub:514|addcore:adder|:127
- 1 B 04 AND2 0 3 0 3 |lpm_add_sub:514|addcore:adder|:135
- 4 B 02 AND2 0 2 0 4 |lpm_add_sub:514|addcore:adder|:139
- 3 B 02 AND2 0 2 0 1 |lpm_add_sub:514|addcore:adder|:143
- 5 B 02 AND2 0 4 0 2 |lpm_add_sub:514|addcore:adder|:151
- 7 B 06 AND2 0 2 0 3 |lpm_add_sub:514|addcore:adder|:155
- 5 B 06 AND2 0 3 0 4 |lpm_add_sub:514|addcore:adder|:163
- 6 B 03 AND2 0 3 0 1 |lpm_add_sub:514|addcore:adder|:171
- 2 B 03 AND2 0 4 0 3 |lpm_add_sub:514|addcore:adder|:175
- 6 B 05 AND2 0 3 0 2 |lpm_add_sub:514|addcore:adder|:183
- 6 B 06 OR2 s 0 3 0 1 ~10~1
- 4 B 03 OR2 s 0 3 0 1 ~10~2
- 1 B 06 OR2 s 0 4 0 2 ~10~3
- 4 B 05 OR2 s 0 3 0 1 ~10~4
- 3 B 05 OR2 s 0 3 0 1 ~10~5
- 1 B 05 OR2 ! 0 4 0 19 :10
- 5 B 05 DFF + 0 3 0 2 ddd19 (:77)
- 7 B 05 DFF + 0 2 0 3 ddd18 (:78)
- 2 B 05 DFF + 0 3 0 3 ddd17 (:79)
- 1 B 07 DFF + 0 2 0 4 ddd16 (:80)
- 5 B 03 DFF + 0 2 0 2 ddd15 (:81)
- 1 B 03 DFF + 0 3 0 4 ddd14 (:82)
- 3 B 03 DFF + 0 2 0 4 ddd13 (:83)
- 2 B 06 DFF + 0 3 0 2 ddd12 (:84)
- 4 B 06 DFF + 0 2 0 3 ddd11 (:85)
- 3 B 06 DFF + 0 2 0 2 ddd10 (:86)
- 1 B 02 DFF + 0 3 0 3 ddd9 (:87)
- 6 B 02 DFF + 0 3 0 3 ddd8 (:88)
- 2 B 02 DFF + 0 2 0 4 ddd7 (:89)
- 1 B 08 DFF + 0 2 0 2 ddd6 (:90)
- 5 B 04 DFF + 0 3 0 2 ddd5 (:91)
- 7 B 04 DFF + 0 2 0 3 ddd4 (:92)
- 8 B 04 DFF + 0 3 0 2 ddd3 (:93)
- 6 B 04 DFF + 0 2 0 3 ddd2 (:94)
- 1 B 12 DFF + 0 2 0 2 ddd1 (:95)
- 5 A 01 DFF + 0 0 0 3 ddd0 (:96)
- 8 B 05 OR2 s ! 0 4 0 1 ~97~1
- 7 A 01 OR2 s ! 0 4 0 1 ~97~2
- 2 B 04 OR2 s ! 0 4 0 1 ~97~3
- 8 A 01 OR2 ! 0 4 0 4 :97
- 3 A 01 DFF + 0 3 0 9 in3 (:121)
- 4 A 01 DFF + 0 3 0 10 in2 (:122)
- 2 A 01 DFF + 0 2 0 11 in1 (:123)
- 1 A 01 DFF + 0 1 0 12 in0 (:124)
- 5 A 11 OR2 s ! 0 4 0 2 ~479~1
- 2 A 12 AND2 ! 0 3 0 8 :479
- 1 A 08 OR2 s 0 4 0 4 ~489~1
- 8 A 11 OR2 s 0 4 0 2 ~489~2
- 5 A 07 OR2 s 0 4 0 2 ~489~3
- 4 A 11 OR2 s 0 3 0 2 ~489~4
- 7 A 11 OR2 s 0 2 0 2 ~489~5
- 5 A 10 OR2 s 0 2 0 1 ~489~6
- 4 A 03 OR2 s 0 4 0 2 ~489~7
- 3 A 13 OR2 s 0 2 0 1 ~489~8
- 2 A 13 OR2 0 3 1 0 :489
- 4 A 10 OR2 s ! 0 4 0 2 ~492~1
- 3 A 10 AND2 s ! 0 2 0 2 ~492~2
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