_LC4_B5  = LCELL( _EQ039);
  _EQ039 =  _LC1_B6
         # !ddd9
         # !ddd14;

-- Node name is '~10~5' 
-- Equation name is '~10~5', location is LC3_B5, type is buried.
-- synthesized logic cell 
_LC3_B5  = LCELL( _EQ040);
  _EQ040 = !ddd17
         # !ddd18
         # !ddd19;

-- Node name is ':10' 
-- Equation name is '_LC1_B5', type is buried 
!_LC1_B5 = _LC1_B5~NOT;
_LC1_B5~NOT = LCELL( _EQ041);
  _EQ041 =  _LC4_B5
         # !ddd16
         #  _LC3_B5
         # !_LC1_B4;

-- Node name is '~97~1' 
-- Equation name is '~97~1', location is LC8_B5, type is buried.
-- synthesized logic cell 
!_LC8_B5 = _LC8_B5~NOT;
_LC8_B5~NOT = LCELL( _EQ042);
  _EQ042 =  ddd1
         #  ddd2
         #  ddd18
         #  ddd17;

-- Node name is '~97~2' 
-- Equation name is '~97~2', location is LC7_A1, type is buried.
-- synthesized logic cell 
!_LC7_A1 = _LC7_A1~NOT;
_LC7_A1~NOT = LCELL( _EQ043);
  _EQ043 =  ddd14
         #  ddd16
         #  ddd9
         #  ddd0;

-- Node name is '~97~3' 
-- Equation name is '~97~3', location is LC2_B4, type is buried.
-- synthesized logic cell 
!_LC2_B4 = _LC2_B4~NOT;
_LC2_B4~NOT = LCELL( _EQ044);
  _EQ044 =  ddd5
         #  ddd19
         #  ddd4
         #  ddd3;

-- Node name is ':97' 
-- Equation name is '_LC8_A1', type is buried 
!_LC8_A1 = _LC8_A1~NOT;
_LC8_A1~NOT = LCELL( _EQ045);
  _EQ045 = !_LC8_B5
         # !_LC7_A1
         # !_LC2_B4
         #  _LC1_B6;

-- Node name is '~479~1' 
-- Equation name is '~479~1', location is LC5_A11, type is buried.
-- synthesized logic cell 
!_LC5_A11 = _LC5_A11~NOT;
_LC5_A11~NOT = LCELL( _EQ046);
  _EQ046 =  in0 &  in1 & !in2 & !in3
         # !in0 & !in1 &  in2 &  in3;

-- Node name is ':479' 
-- Equation name is '_LC2_A12', type is buried 
!_LC2_A12 = _LC2_A12~NOT;
_LC2_A12~NOT = LCELL( _EQ047);
  _EQ047 = !_LC1_A8 & !_LC3_A6 & !_LC3_A11;

-- Node name is '~489~1' 
-- Equation name is '~489~1', location is LC1_A8, type is buried.
-- synthesized logic cell 
_LC1_A8  = LCELL( _EQ048);
  _EQ048 =  in0 &  in1 & !in2 &  in3
         # !in0 & !in1 &  in2 & !in3;

-- Node name is '~489~2' 
-- Equation name is '~489~2', location is LC8_A11, type is buried.
-- synthesized logic cell 
_LC8_A11 = LCELL( _EQ049);
  _EQ049 =  in0 & !in1 & !in2 &  in3
         # !in0 &  in1 &  in2 & !in3;

-- Node name is '~489~3' 
-- Equation name is '~489~3', location is LC5_A7, type is buried.
-- synthesized logic cell 
_LC5_A7  = LCELL( _EQ050);
  _EQ050 =  in0 & !in1 & !in2 & !in3
         # !in0 &  in1 &  in2 &  in3;

-- Node name is '~489~4' 
-- Equation name is '~489~4', location is LC4_A11, type is buried.
-- synthesized logic cell 
_LC4_A11 = LCELL( _EQ051);
  _EQ051 =  _LC8_A11
         #  _LC3_A6
         #  _LC1_A8;

-- Node name is '~489~5' 
-- Equation name is '~489~5', location is LC7_A11, type is buried.
-- synthesized logic cell 
_LC7_A11 = LCELL( _EQ052);
  _EQ052 = !_LC5_A11
         #  _LC4_A11;

-- Node name is '~489~6' 
-- Equation name is '~489~6', location is LC5_A10, type is buried.
-- synthesized logic cell 
_LC5_A10 = LCELL( _EQ053);
  _EQ053 =  _LC2_A10
         #  _LC7_A11;

-- Node name is '~489~7' 
-- Equation name is '~489~7', location is LC4_A3, type is buried.
-- synthesized logic cell 
_LC4_A3  = LCELL( _EQ054);
  _EQ054 =  in1 & !in2 & !in3
         # !in1 &  in2 &  in3
         # !in0 &  in1 & !in2
         #  in0 & !in1 &  in2
         #  in0 &  in3
         # !in0 & !in3;

-- Node name is '~489~8' 
-- Equation name is '~489~8', location is LC3_A13, type is buried.
-- synthesized logic cell 
_LC3_A13 = LCELL( _EQ055);
  _EQ055 =  _LC3_A6
         #  _LC1_A8;

-- Node name is ':489' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = LCELL( _EQ056);
  _EQ056 = !_LC2_A12 &  _LC2_A13
         #  _LC4_A3
         #  _LC5_A7;

-- Node name is '~492~1' 
-- Equation name is '~492~1', location is LC4_A10, type is buried.
-- synthesized logic cell 
!_LC4_A10 = _LC4_A10~NOT;
_LC4_A10~NOT = LCELL( _EQ057);
  _EQ057 = !in1 &  in2
         #  in1 & !in2
         # !in0 &  in2 & !in3
         # !in0 &  in1 & !in3
         #  in0 & !in1 &  in3
         #  in0 & !in2 &  in3;

-- Node name is '~492~2' 
-- Equation name is '~492~2', location is LC3_A10, type is buried.
-- synthesized logic cell 
!_LC3_A10 = _LC3_A10~NOT;
_LC3_A10~NOT = LCELL( _EQ058);
  _EQ058 = !_LC2_A10 & !_LC4_A10;

-- Node name is '~492~3' 
-- Equation name is '~492~3', location is LC6_A11, type is buried.
-- synthesized logic cell 
!_LC6_A11 = _LC6_A11~NOT;
_LC6_A11~NOT = LCELL( _EQ059);
  _EQ059 = !_LC3_A10 &  _LC5_A11;

-- Node name is '~492~4' 
-- Equation name is '~492~4', location is LC4_A9, type is buried.
-- synthesized logic cell 
_LC4_A9  = LCELL( _EQ060);
  _EQ060 = !in0 & !in1 & !in2 &  in3
         #  in0 &  in1 &  in2 & !in3;

-- Node name is '~492~5' 
-- Equation name is '~492~5', location is LC3_A9, type is buried.
-- synthesized logic cell 
_LC3_A9  = LCELL( _EQ061);
  _EQ061 =  _LC5_A7
         #  _LC4_A9;

-- Node name is ':492' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ062);
  _EQ062 =  _LC1_A13 & !_LC2_A12
         #  _LC3_A13
         #  _LC6_A11;

-- Node name is '~495~1' 
-- Equation name is '~495~1', location is LC3_A11, type is buried.
-- synthesized logic cell 
!_LC3_A11 = _LC3_A11~NOT;
_LC3_A11~NOT = LCELL( _EQ063);
  _EQ063 = !_LC6_A11 & !_LC8_A11;

-- Node name is ':495' 
-- Equation name is '_LC1_A12', type is buried 
_LC1_A12 = LCELL( _EQ064);
  _EQ064 =  _LC1_A12 & !_LC2_A12
         #  _LC3_A11
         #  _LC1_A8;

-- Node name is '~498~1' 
-- Equation name is '~498~1', location is LC3_A6, type is buried.
-- synthesized logic cell 
_LC3_A6  = LCELL( _EQ065);
  _EQ065 = !in0 &  in1 & !in2 &  in3
         #  in0 & !in1 &  in2 & !in3;

-- Node name is ':498' 
-- Equation name is '_LC2_A11', type is buried 
_LC2_A11 = LCELL( _EQ066);
  _EQ066 =  _LC3_A11
         #  _LC3_A6
         #  _LC2_A11 & !_LC2_A12;

-- Node name is '~501~1' 
-- Equation name is '~501~1', location is LC2_A10, type is buried.
-- synthesized logic cell 
_LC2_A10 = LCELL( _EQ067);
  _EQ067 = !in0 &  in1 & !in2 & !in3
         #  in0 & !in1 &  in2 &  in3;

-- Node name is ':501' 
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = LCELL( _EQ068);
  _EQ068 =  _LC1_A11 & !_LC2_A12
         #  _LC3_A10
         #  _LC4_A11;

-- Node name is ':504' 
-- Equation name is '_LC1_A10', type is buried 
_LC1_A10 = LCELL( _EQ069);
  _EQ069 =  _LC1_A10 & !_LC2_A12
         #  _LC4_A10
         #  _LC7_A11;

-- Node name is ':507' 
-- Equation name is '_LC2_A9', type is buried 
_LC2_A9  = LCELL( _EQ070);
  _EQ070 =  _LC2_A9 & !_LC2_A12
         #  _LC4_A3
         #  _LC4_A9;

-- Node name is ':510' 
-- Equation name is '_LC1_A9', type is buried 
_LC1_A9  = LCELL( _EQ071);
  _EQ071 =  _LC1_A9 & !_LC2_A12
         #  _LC3_A9
         #  _LC5_A10;



Project Informatione:\wintools\programer\maxplus2\mydesign\homeworks\lead1\cc1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX8000' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 6,349K