`include "defs.h"module input_signal(out, reset, clk);output [16-1:0]out;input  reset, clk;reg    [`S-1:0] enc_bit01, enc_bit02, enc_bit11, enc_bit12;assign out = {enc_bit01, enc_bit02, enc_bit11, enc_bit12};initial	begin	`include "in_signal.v"	endendmodulemodule test;/////////////wire [16-1:0] encoded_signal;reg  [1:0]  sel_enc;reg         clk, reset;wire [3:0] decoded_signal;input_signal is(encoded_signal, reset, clk);decoder dec(encoded_signal, decoded_signal, reset, clk);/////////always #20 clk = ~clk;///////////always @(posedge clk)    $display(,, "decoded_signal : %b", decoded_signal, "\n");initial	begin//	$shm_open("waves.shm");//	$shm_probe(test, "AS");		clk = 0;	reset = 1;	@(posedge clk)	@(posedge clk)		reset = #5 0;	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)//	$shm_close();	$finish;	end	endmodule