`include "defs.h"module decoder(encoded_signal,  bit_line,  reset,  clk);input  [48-1:0] encoded_signal;input           reset;output [11:0]  bit_line;input clk;wire  [`S-1:0] sum_enc_bits0,  sub_enc_bits0,  sum_enc_bits1,  sub_enc_bits1,  sum_enc_bits2,  sub_enc_bits2,                 sum_enc_bits3,  sub_enc_bits3,  sum_enc_bits4,  sub_enc_bits4,  sum_enc_bits5,  sub_enc_bits5;wire  [48-1:0] cmp;reg   [48-1:0] cmp0,  cmp1,  cmp2;reg   [96-1:0] b_cmp0,  b_cmp1;wire  restart;block blk(sum_enc_bits0,  sub_enc_bits0,  sum_enc_bits1,  sub_enc_bits1,  sum_enc_bits2,  sub_enc_bits2,                 sum_enc_bits3,  sub_enc_bits3,  sum_enc_bits4,  sub_enc_bits4,  sum_enc_bits5,  sub_enc_bits5,  cmp,  reset,  clk);backtrack bt(b_cmp0,  restart,  clk,  bit_line);assign sum_enc_bits0 = encoded_signal[47:44] + encoded_signal[43:40];assign sub_enc_bits0 = encoded_signal[47:44] - encoded_signal[43:40];assign sum_enc_bits1 = encoded_signal[39:36] + encoded_signal[35:32];assign sub_enc_bits1 = encoded_signal[39:36] - encoded_signal[35:32];assign sum_enc_bits2 = encoded_signal[31:28] + encoded_signal[27:24];assign sub_enc_bits2 = encoded_signal[31:28] - encoded_signal[27:24];assign sum_enc_bits3 = encoded_signal[23:20] + encoded_signal[19:16];assign sub_enc_bits3 = encoded_signal[23:20] - encoded_signal[19:16];assign sum_enc_bits4 = encoded_signal[15:12] + encoded_signal[11:8];assign sub_enc_bits4 = encoded_signal[15:12] - encoded_signal[11:8];assign sum_enc_bits5 = encoded_signal[7:4] + encoded_signal[3:0];assign sub_enc_bits5 = encoded_signal[7:4] - encoded_signal[3:0];always @(posedge clk) cmp2 = #5 cmp1;always @(posedge clk) cmp1 = #5 cmp0;always @(posedge clk) cmp0 = #5 cmp;always @(posedge clk) b_cmp0 = #5 restart == 1 ? {cmp ,  cmp0} : b_cmp1;always @(posedge clk) b_cmp1 = #5 {cmp1,  cmp2};reg cnt;assign restart = cnt == 1;always @(posedge clk)       if (reset == 1) cnt = 0;       else if (cnt == 1) cnt = 0;            else cnt = cnt + 1;endmodule