`include "defs.h"module input_signal(out,  reset,  clk);output [64-1:0]out;input  reset,  clk;reg    [`S-1:0] enc_bit01,  enc_bit02,  enc_bit11,  enc_bit12,  enc_bit21,  enc_bit22,  enc_bit31,  enc_bit32,  enc_bit41,  enc_bit42,  enc_bit51,  enc_bit52,  enc_bit61,  enc_bit62,  enc_bit71,  enc_bit72;assign out = {enc_bit01,  enc_bit02,  enc_bit11,  enc_bit12,  enc_bit21,  enc_bit22,  enc_bit31,  enc_bit32,  enc_bit41,  enc_bit42,  enc_bit51,  enc_bit52,  enc_bit61,  enc_bit62,  enc_bit71,  enc_bit72};initial	begin	`include "in_signal.v"	endendmodulemodule test;/////////////wire [64-1:0] encoded_signal;reg  [1:0]  sel_enc;reg         clk,  reset;wire [7:0] decoded_signal;input_signal is(encoded_signal,  reset,  clk);decoder dec(encoded_signal,  decoded_signal,  reset,  clk);/////////always #20 clk = ~clk;///////////always @(posedge clk)    $display(, ,  "decoded_signal : %b",  decoded_signal,  "\n");initial	begin//	$shm_open("waves.shm");//	$shm_probe(test,  "AS");		clk = 0;	reset = 1;	@(posedge clk)	@(posedge clk)		reset = #5 0;	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)	@(posedge clk)//	$shm_close();	$finish;	end	endmodule