?? cfcard.h
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/***************************************************************************
* File: cfcard.h - Common definition for CF Card
*
* The content of this file or document is CONFIDENTIAL and PROPRIETARY
* to Jade Technologies Co., Ltd. It is subject to the terms of a
* License Agreement between Licensee and Jade Technologies Co., Ltd.
* restricting among other things, the use, reproduction, distribution
* and transfer. Each of the embodiments, including this information
* and any derivative work shall retain this copyright notice.
*
* Copyright (c) 2005 Jade Technologies Co., Ltd.
* All rights reserved.
****************************************************************************/
#ifndef CFCARD_H
#define CFCARD_H
#include <windows.h>
#include <ceddk.h>
#include <types.h>
#include <excpt.h>
#include <tchar.h>
#include <devload.h>
#include <diskio.h>
#include <storemgr.h>
#include <pkfuncs.h>
#include <oalfuncs.h>
#include "OalIntr.h"
#include "dma.h"
//------------------------------------------------------------------------------
//
// Global Macros
//
//------------------------------------------------------------------------------
// MSG definition
#define MSG_SYS 0
#define MSG_DISK 0
#define MSG_INFO 0
#define MSG_PAP 0
#define MSG_DATA 0
#define MSG_DMA 0
// Test definition, if 1, card get into test mode.
#define CF_TEST 0
// common definition
#define CF_HOST_BASE_ADDRESS 0x2000e000
#define CF_BURST_BYTES 0x00000040
#define SECTORS_PER_BATCH 0x00000080
#define BYTES_PER_SECTOR 0x00000200
#define SECTORS_NEED_DMA_READ 0 //not use DMA 0xff
#define SECTORS_NEED_DMA_WRITE 0
#define SleepCircle 0x10
// DISK.d_DiskCardState
#define STATE_INITING 1
#define STATE_CLOSED 2
#define STATE_OPENED 3
#define STATE_DEAD 4 // Power down
#define STATE_REMOVED 5
// FIFO request
#define FIFOreq_TXPush 0x00
#define FIFOreq_TXPop 0x01
#define FIFOreq_RXPop 0x02
#define FIFOreq_RXPush 0x03
#define FIFOreq_FifoInc 0x04
#define FIFOreq_FifoStep 0x05
#define FIFOreq_DataEn 0x07
#define FIFOreq_IntrClr 0x08
#define FIFOreq_FifoCntClr 0x09
#define FIFOreq_StopFifo 0x0a
#define FIFOreq_ClearFifo 0x0b
#define FIFOreq_DmaTxReq 0x0c
#define FIFOreq_DmaRxReq 0x0d
// cfcard status
#define CfStatus_ready 0
#define CfStatus_wait_b 1
#define CfStatus_wp 2
#define CfStatus_TxRunning 4
#define CfStatus_TxHalf 5
#define CfStatus_TxFull 6
#define CfStatus_TxEmpty 7
#define CfStatus_RxRunning 8
#define CfStatus_RxHalf 9
#define CfStatus_RxFull 10
#define CfStatus_RxEmpty 11
#define CfStatus_Underrun 12
#define CfStatus_Overrun 13
// cf card work mode
#define CFMODE_MEMORY 0x1e
#define CFMODE_IO 0x1d
#define CFMODE_ATTRIB 0x1b
#define CFMODE_IDE 0x17
#define CFMODE_IDEALT 0x0f
// r/w mask bits
#define CfValidByte0 0x0e
#define CfValidByte1 0x0d
#define CfValidByte2 0x0b
#define CfValidByte3 0x07
// adapter register offset
#define CfU_Signal_cf 0
#define CfU_Signal_forceide 1
#define CfU_Signal_cs_b 2
#define CfU_Signal_blast_b 7
#define CfU_Signal_be_b 8
// interrupt bit
#define CfRawIntr_PCMInsert 0
#define CfRawIntr_PCMRemove 1
#define CfRawIntr_CfInsert 2
#define CfRawIntr_CfRemove 3
#define CfRawIntr_TxPushOver 4
#define CfRawIntr_TxPopOver 5
#define CfRawIntr_RxPushOver 6
#define CfRawIntr_RxPopOver 7
#define CfRawIntr_FifoOverrun 8
#define CfRawIntr_FifoUnderrun 9
#define CfRowIntr_IllegalWrite 10
#define CfRowIntr_IllegalRead 11
#define CfRawIntr_IOIrq 12
#define CfRawIntr_IDEIrq 13
#define CfRawIntr_CardAbsent 14
#define CfRawIntr_RWConflict 15
#define CfRawIntr_TxfifoHfReq 16
#define CfRawIntr_RxfifoHfReq 17
#define CF_DATA_INTR_MASK \
((1 << CfRawIntr_TxPopOver) \
|(1 << CfRawIntr_RxPopOver) \
|(1 << CfRawIntr_TxfifoHfReq) \
|(1 << CfRawIntr_RxfifoHfReq))
// card register offset(32bits)
#define ATA_REG_DATA 0
#define ATA_REG_FEATURE 1 // write
#define ATA_REG_ERROR 1 // read
#define ATA_REG_SECT_CNT 2
#define ATA_REG_SECT_NUM 3
#define ATA_REG_CYL_LOW 4
#define ATA_REG_CYL_HIGH 5
#define ATA_REG_DRV_HEAD 6
#define ATA_REG_COMMAND 7 // write
#define ATA_REG_STATUS 7 // read
// command
#define ATA_CMD_READ 0x20 // NO retries enabled
#define ATA_CMD_WRITE 0x30 // No retries enabled
#define ATA_CMD_IDENTIFY 0xEC
// limit sectors r/w no more than 0xff one time
#define SetRegSectorConfig(reg, Num) {reg = 0x7f00 + Num;}
// DMAC address
#define DMAC_BASE (0x20001000)
// DMAC channel config register
#define DMAC_CHCONFIG_H 0x00040000 // Halt transfer
#define DMAC_CHCONFIG_A 0x00020000 // Channel is active
#define DMAC_CHCONFIG_L 0x00010000 // Lock transfer
#define DMAC_CHCONFIG_ITC 0x00008000 // Terminal count interrupt enable
#define DMAC_CHCONFIG_IE 0x00004000 // Error interrupt enable
#define DMAC_CHCONFIG_FLOW 0x00003800 // Flow control
#define DMAC_CHCONFIG_DPER 0x000003C0 // Destination peripheral
#define DMAC_CHCONFIG_SPER 0x0000001E // Source peripheral
#define DMAC_CHCONFIG_E 0x00000001 // Channel enable
// DMAC channel control register bit masks
#define DMAC_CTRL_I 0x80000000 // Terminal count interrupt enable
#define DMAC_CTRL_CACHE 0x40000000 // Cacheable
#define DMAC_CTRL_BUF 0x20000000 // Bufferable
#define DMAC_CTRL_PRIV 0x10000000 // Privileged
#define DMAC_CTRL_DI 0x08000000 // Destination increment
#define DMAC_CTRL_SI 0x04000000 // Source increment
#define DMAC_CTRL_D 0x02000000 // Dest master select
#define DMAC_CTRL_S 0x01000000 // Source master select
#define DMAC_DWIDTH 0x00E00000 // Destination width
#define DMAC_SWIDTH 0x001C0000 // Source width
#define DMAC_DBSIZE 0x00038000 // Dest burst size
#define DMAC_SBSIZE 0x00007000 // Source burst size
#define DMAC_TRANSFER_SIZE 0x00000FFF // Transfer size
// These are the transfer width ids
#define TRANSFER_WIDTH_BYTE 0x000
#define TRANSFER_WIDTH_WORD 0x001
#define TRANSFER_WIDTH_DWORD 0x002
#define DMAC_DWIDTH_SHIFT 21
#define DMAC_SWIDTH_SHIFT 18
#define DMAC_DBSIZE_SHIFT 15
#define DMAC_SBSIZE_SHIFT 12
// These are the burst size ids
#define BURST_SIZE_1 0x000
#define BURST_SIZE_4 0x001
#define BURST_SIZE_8 0x002
#define BURST_SIZE_16 0x003
#define BURST_SIZE_32 0x004
#define BURST_SIZE_64 0x005
#define BURST_SIZE_128 0x006
#define BURST_SIZE_256 0x007
#define DMAC_FLOW_SHIFT 11
#define DMAC_DPER_SHIFT 6
#define DMAC_SPER_SHIFT 1
#define FLOW_MEM_MEM_DMAC 0x000 // Memory to memory - DMAC as flow controller
#define FLOW_MEM_PER_DMAC 0x001 // Memory to peripheral - DMAC as flow controller
#define FLOW_PER_MEM_DMAC 0x002 // Peripheral to memory - DMAC as flow controller
#define FLOW_PER_PER_DMAC 0x003 // Peripheral to peripheral - DMAC as flow controller
#define FLOW_PER_PER_DEST 0x004 // Peripheral to peripheral - destination peripheral as flow controller
#define FLOW_MEM_PER_DEST 0x005 // Memory to peripheral - destination peripheral as flow controller
#define FLOW_PER_MEM_SOURCE 0x006 // Peripheral to memory - source peripheral as flow controller
#define FLOW_PER_PER_SOURCE 0x007 // Peripheral to peripheral - source peripheral as flow controller
//------------------------------------------------------------------------------
//
// Structures
//
//------------------------------------------------------------------------------
typedef volatile struct
{
unsigned long CF_ADDR_FIFOreq ;
unsigned long CF_ADDR_TXFIFOCnt ;
unsigned long CF_ADDR_RXFIFOCnt ;
unsigned long CF_ADDR_u_fifoaddr ;
unsigned long CF_ADDR_SectorCfg ;
unsigned long CF_ADDR_CfStatus ;
unsigned long CF_ADDR_CfBaseAddr ;
unsigned long CF_ADDR_CfAddr ;
unsigned long CF_ADDR_CfData ;
unsigned long CF_ADDR_CfResult ;
unsigned long CF_ADDR_CFReset ;
unsigned long CF_ADDR_config_val ;
unsigned long CF_ADDR_u_signal ;
unsigned long CF_ADDR_u_sig_eff ;
unsigned long CF_ADDR_CardIns ;
unsigned long CF_ADDR_CFINTR ;
unsigned long CF_ADDR_CFINTM ;
unsigned long CF_ADDR_CFINTena ;
unsigned long CF_ADDR_VERSION ;
unsigned long Reserve1[ 0x0d ] ;
unsigned long CF_ADDR_FIFO ;
unsigned long Reserve2[0x200-0x20-1] ;
unsigned long CF_BaseADDR_CARD[0x100] ;
} CFRegs, * PCFRegs;
// Data returned by the ATA_CMD_IDENTIFY command
typedef struct _IDENTIFY_DATA {
unsigned short GeneralConfiguration; // 00
unsigned short NumberOfCylinders; // 01
unsigned short Reserved1; // 02
unsigned short NumberOfHeads; // 03
unsigned short UnformattedBytesPerTrack; // 04
unsigned short UnformattedBytesPerSector; // 05
unsigned short SectorsPerTrack; // 06
unsigned short VendorUnique1[3]; // 07
unsigned short SerialNumber[10]; // 10
unsigned short BufferType; // 20
unsigned short BufferSectorSize; // 21
unsigned short NumberOfEccBytes; // 22
unsigned short FirmwareRevision[4]; // 23
unsigned short ModelNumber[20]; // 27
unsigned char MaximumBlockTransfer; // 47 low byte
unsigned char VendorUnique2; // 47 high byte
unsigned short DoubleWordIo; // 48
unsigned short Capabilities; // 49
unsigned short Reserved2; // 50
unsigned char VendorUnique3; // 51 low byte
unsigned char PioCycleTimingMode; // 51 high byte
unsigned char VendorUnique4; // 52 low byte
unsigned char DmaCycleTimingMode; // 52 high byte
unsigned short TranslationFieldsValid; // 53 (low bit)
unsigned short NumberOfCurrentCylinders; // 54
unsigned short NumberOfCurrentHeads; // 55
unsigned short CurrentSectorsPerTrack; // 56
unsigned long CurrentSectorCapacity; // 57 & 58
unsigned char MultiSectorCount; // 59 low
unsigned char MultiSectorSettingValid; // 59 high (low bit)
unsigned long TotalUserAddressableSectors; // 60 & 61
unsigned char SingleDmaModesSupported; // 62 low byte
unsigned char SingleDmaTransferActive; // 62 high byte
unsigned char MultiDmaModesSupported; // 63 low byte
unsigned char MultiDmaTransferActive; // 63 high byte
unsigned short Reserved[192]; // 64
}IDENTIFY_DATA, *PIDENTIFY_DATA;
typedef struct _DISK {
CRITICAL_SECTION d_DiskCardCrit; // guard access to global state and card
unsigned long d_DiskCardState; // indicate card current state
DISK_INFO d_DiskInfo; // for DISK_IOCTL_GET/SETINFO
PCFRegs d_pCFCardRegs; // adapter registers
LPWSTR d_ActivePath; // registry path to active key for this device
}DISK, *PDISK;
typedef struct tagDMACRegisters {
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