library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
    port( clk,rst   : in std_logic;
          clkout	: out std_logic);
end counter;

architecture logic1 of counter is
signal count    : std_logic_vector(7 downto 0);
signal temp		: std_logic;
begin

    process(rst,clk)
    begin
        if (rst = '1') then
            count <= (others => '0');
        elsif(clk'event and clk = '0') then

            if count >= 78 then
                temp <= not(temp);
				count <= (others => '0');
            else
                count <= count + '1';
            end if;

        end if;
    end process;
	clkout <= temp;
end logic1;