?? cis_cpld.rpt
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Project Information c:\max2work\work\cis_cpld6\cis_cpld.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 01/26/2002 10:28:03
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Title: CIS CPLD
Company: CHEIL COMTECH CO., LTD.
Designer: CHEIL COMTECH R&D
Rev: A
Date: 6:24p 1-14-2002
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
cis_cpld EPM7128AETC100-5 33 27 16 87 0 67 %
User Pins: 33 27 16
Project Information c:\max2work\work\cis_cpld6\cis_cpld.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'RAM_A14' is stuck at GND
Project Information c:\max2work\work\cis_cpld6\cis_cpld.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
cis_cpld@84 /ACK
cis_cpld@80 AK_CLK
cis_cpld@79 AK_TRIG
cis_cpld@78 CIS_CLK
cis_cpld@77 CIS_SP
cis_cpld@64 CMOS_D0
cis_cpld@65 CMOS_D1
cis_cpld@67 CMOS_D2
cis_cpld@68 CMOS_D3
cis_cpld@69 CMOS_D4
cis_cpld@70 CMOS_D5
cis_cpld@71 CMOS_D6
cis_cpld@72 CMOS_D7
cis_cpld@1 CPU_A0
cis_cpld@2 CPU_A1
cis_cpld@5 CPU_A2
cis_cpld@6 CPU_A3
cis_cpld@7 CPU_A4
cis_cpld@8 CPU_A5
cis_cpld@9 CPU_A6
cis_cpld@10 CPU_A7
cis_cpld@12 CPU_A8
cis_cpld@13 CPU_A9
cis_cpld@14 CPU_A10
cis_cpld@16 CPU_A11
cis_cpld@17 CPU_A12
cis_cpld@19 CPU_A13
cis_cpld@20 CPU_A19
cis_cpld@21 CPU_A20
cis_cpld@24 /CPU_CS1
cis_cpld@25 /CPU_CS2
cis_cpld@92 CPU_D0
cis_cpld@93 CPU_D1
cis_cpld@94 CPU_D2
cis_cpld@96 CPU_D3
cis_cpld@97 CPU_D4
cis_cpld@98 CPU_D5
cis_cpld@99 CPU_D6
cis_cpld@100 CPU_D7
cis_cpld@22 /CPU_RD
cis_cpld@23 /CPU_WR
cis_cpld@28 /CS10
cis_cpld@29 /CS11
cis_cpld@30 /CS12
cis_cpld@31 /CS13
cis_cpld@27 /FIQ
cis_cpld@85 /IRQ1
cis_cpld@81 MCLK
cis_cpld@50 RAM_A0
cis_cpld@49 RAM_A1
cis_cpld@48 RAM_A2
cis_cpld@47 RAM_A3
cis_cpld@46 RAM_A4
cis_cpld@45 RAM_A5
cis_cpld@44 RAM_A6
cis_cpld@42 RAM_A7
cis_cpld@41 RAM_A8
cis_cpld@40 RAM_A9
cis_cpld@37 RAM_A10
cis_cpld@36 RAM_A11
cis_cpld@35 RAM_A12
cis_cpld@33 RAM_A13
cis_cpld@32 RAM_A14
cis_cpld@52 RAM_D0
cis_cpld@53 RAM_D1
cis_cpld@54 RAM_D2
cis_cpld@55 RAM_D3
cis_cpld@56 RAM_D4
cis_cpld@57 RAM_D5
cis_cpld@58 RAM_D6
cis_cpld@60 RAM_D7
cis_cpld@61 /RAM_RD
cis_cpld@63 /RAM_WR
cis_cpld@76 /SENSOR_IN
cis_cpld@75 TCLK
cis_cpld@83 /TRIG-A
Project Information c:\max2work\work\cis_cpld6\cis_cpld.rpt
** FILE HIERARCHY **
|74157:11|
|74157:12|
|74157:3|
|74157:2|
|74157:204|
|74244:68|
|74244:77|
|74244:78|
|74161:276|
|74161:276|p74161:sub|
|test3:328|
|test3:328|counter:44|
|test3:328|counter:44|lpm_add_sub:157|
|test3:328|counter:44|lpm_add_sub:157|addcore:adder|
|test3:328|counter:44|lpm_add_sub:157|altshift:result_ext_latency_ffs|
|test3:328|counter:44|lpm_add_sub:157|altshift:carry_ext_latency_ffs|
|test3:328|counter:44|lpm_add_sub:157|altshift:oflow_ext_latency_ffs|
|counter1:407|
|74138:408|
Device-Specific Information: c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld
***** Logic for device 'cis_cpld' compiled without errors.
Device: EPM7128AETC100-5
Device Options:
Turbo Bit = OFF
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
Device-Specific Information: c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld
** ERROR SUMMARY **
Info: Chip 'cis_cpld' in device 'EPM7128AETC100-5' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
/
S
E
/ A C N
C C C C C C C C V T A K I C S
P P P P P P P P C / R V K _ S I O
U U U U U U U U C I / I C M _ T _ S R
_ _ _ _ _ G _ _ _ I G G G G G R A G C C C R C _ _
D D D D D N D D D N N N N N N Q C - I L L I L S I
7 6 5 4 3 D 2 1 0 T D D D D D 1 K A O K K G K P N
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
CPU_A0 | 1 75 | TCLK
CPU_A1 | 2 74 | GND
VCCIO | 3 73 | #TDO
#TDI | 4 72 | CMOS_D7
CPU_A2 | 5 71 | CMOS_D6
CPU_A3 | 6 70 | CMOS_D5
CPU_A4 | 7 69 | CMOS_D4
CPU_A5 | 8 68 | CMOS_D3
CPU_A6 | 9 67 | CMOS_D2
CPU_A7 | 10 66 | VCCIO
GND | 11 65 | CMOS_D1
CPU_A8 | 12 64 | CMOS_D0
CPU_A9 | 13 EPM7128AETC100-5 63 | /RAM_WR
CPU_A10 | 14 62 | #TCK
#TMS | 15 61 | /RAM_RD
CPU_A11 | 16 60 | RAM_D7
CPU_A12 | 17 59 | GND
VCCIO | 18 58 | RAM_D6
CPU_A13 | 19 57 | RAM_D5
CPU_A19 | 20 56 | RAM_D4
CPU_A20 | 21 55 | RAM_D3
/CPU_RD | 22 54 | RAM_D2
/CPU_WR | 23 53 | RAM_D1
/CPU_CS1 | 24 52 | RAM_D0
/CPU_CS2 | 25 51 | VCCIO
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
N F C C C C A A C A A A N C A A A N A A A A A A A
D I S S S S M M C M M M D C M M M D M M M M M M M
Q 1 1 1 1 _ _ I _ _ _ I _ _ _ _ _ _ _ _ _ _
0 1 2 3 A A O A A A N A A A A A A A A A A
1 1 1 1 1 T 9 8 7 6 5 4 3 2 1 0
4 3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GND* = These I/O pins can either be left unconnected or connected to GND. Connecting these pins to GND will improve the device's immunity to noise.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld
** RESOURCE USAGE **
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