?? cis_cpld.rpt
字號:
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 10/16( 62%) 10/10(100%) 0/16( 0%) 14/36( 38%)
B: LC17 - LC32 7/16( 43%) 10/10(100%) 0/16( 0%) 18/36( 50%)
C: LC33 - LC48 16/16(100%) 10/10(100%) 9/16( 56%) 16/36( 44%)
D: LC49 - LC64 10/16( 62%) 10/10(100%) 0/16( 0%) 24/36( 66%)
E: LC65 - LC80 10/16( 62%) 10/10(100%) 0/16( 0%) 21/36( 58%)
F: LC81 - LC96 9/16( 56%) 10/10(100%) 0/16( 0%) 19/36( 52%)
G: LC97 - LC112 9/16( 56%) 10/10(100%) 0/16( 0%) 16/36( 44%)
H: LC113 - LC128 16/16(100%) 10/10(100%) 0/16( 0%) 16/36( 44%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 80/80 (100%)
Total logic cells used: 87/128 ( 67%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 0/128 ( 0%)
Total shareable expanders not available (n/a): 9/128 ( 7%)
Average fan-in: 5.19
Total fan-in: 452
Total input pins required: 33
Total fast input logic cells required: 0
Total output pins required: 27
Total bidirectional pins required: 16
Total reserved pins required 4
Total logic cells required: 87
Total flipflops required: 39
Total product terms required: 201
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 3/ 128 ( 2%)
Device-Specific Information: c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
84 (126) (H) INPUT 0 0 0 0 0 0 1 /ACK
64 (99) (G) INPUT 0 0 0 0 0 1 0 CMOS_D0
65 (101) (G) INPUT 0 0 0 0 0 1 0 CMOS_D1
67 (102) (G) INPUT 0 0 0 0 0 1 0 CMOS_D2
68 (104) (G) INPUT 0 0 0 0 0 1 0 CMOS_D3
69 (105) (G) INPUT 0 0 0 0 0 1 0 CMOS_D4
70 (107) (G) INPUT 0 0 0 0 0 1 0 CMOS_D5
71 (109) (G) INPUT 0 0 0 0 0 1 0 CMOS_D6
72 (110) (G) INPUT 0 0 0 0 0 1 0 CMOS_D7
1 (3) (A) INPUT 0 0 0 0 0 1 0 CPU_A0
2 (1) (A) INPUT 0 0 0 0 0 1 0 CPU_A1
5 (30) (B) INPUT 0 0 0 0 0 1 0 CPU_A2
6 (29) (B) INPUT 0 0 0 0 0 1 0 CPU_A3
7 (27) (B) INPUT 0 0 0 0 0 1 0 CPU_A4
8 (25) (B) INPUT 0 0 0 0 0 1 0 CPU_A5
9 (24) (B) INPUT 0 0 0 0 0 1 0 CPU_A6
10 (22) (B) INPUT 0 0 0 0 0 1 0 CPU_A7
12 (21) (B) INPUT 0 0 0 0 0 1 0 CPU_A8
13 (19) (B) INPUT 0 0 0 0 0 1 0 CPU_A9
14 (17) (B) INPUT 0 0 0 0 0 1 0 CPU_A10
16 (46) (C) INPUT 0 0 0 0 0 1 0 CPU_A11
17 (45) (C) INPUT 0 0 0 0 0 1 0 CPU_A12
19 (43) (C) INPUT 0 0 0 0 0 1 0 CPU_A13
20 (41) (C) INPUT 0 0 0 0 0 4 0 CPU_A19
21 (40) (C) INPUT 0 0 0 0 0 4 0 CPU_A20
24 (35) (C) INPUT 0 0 0 0 0 4 0 /CPU_CS1
25 (33) (C) INPUT 0 0 0 0 0 24 2 /CPU_CS2
92 16 A BIDIR 0 0 0 0 1 1 0 CPU_D0
93 14 A BIDIR 0 0 0 0 1 1 0 CPU_D1
94 13 A BIDIR 0 0 0 0 1 1 0 CPU_D2
96 11 A BIDIR 0 0 0 0 1 1 0 CPU_D3
97 9 A BIDIR 0 0 0 0 1 1 0 CPU_D4
98 8 A BIDIR 0 0 0 0 1 1 0 CPU_D5
99 6 A BIDIR 0 0 0 0 1 1 0 CPU_D6
100 5 A BIDIR 0 0 0 0 1 1 0 CPU_D7
22 (38) (C) INPUT 0 0 0 0 0 1 1 /CPU_RD
23 (37) (C) INPUT 0 0 0 0 0 9 1 /CPU_WR
81 (123) (H) INPUT 0 0 0 0 0 1 0 MCLK
52 81 F BIDIR 0 0 0 3 1 1 0 RAM_D0
53 83 F BIDIR 0 0 0 3 1 1 0 RAM_D1
54 85 F BIDIR 0 0 0 3 1 1 0 RAM_D2
55 86 F BIDIR 0 0 0 3 1 1 0 RAM_D3
56 88 F BIDIR 0 0 0 3 1 1 0 RAM_D4
57 89 F BIDIR 0 0 0 3 1 1 0 RAM_D5
58 91 F BIDIR 0 0 0 3 1 1 0 RAM_D6
60 93 F BIDIR 0 0 0 3 1 1 0 RAM_D7
76 (115) (H) INPUT 0 0 0 0 0 0 1 /SENSOR_IN
75 (113) (H) INPUT 0 0 0 0 0 1 14 TCLK
83 (125) (H) INPUT 0 0 0 0 0 1 0 /TRIG-A
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
80 121 H FF 0 0 0 1 0 2 4 AK_CLK
79 120 H FF 0 0 0 0 3 0 0 AK_TRIG
78 118 H OUTPUT 0 0 0 0 4 0 0 CIS_CLK
77 117 H FF ! h 0 0 0 0 3 1 14 CIS_SP
92 16 A TRI 0 0 0 0 1 1 0 CPU_D0
93 14 A TRI 0 0 0 0 1 1 0 CPU_D1
94 13 A TRI 0 0 0 0 1 1 0 CPU_D2
96 11 A TRI 0 0 0 0 1 1 0 CPU_D3
97 9 A TRI 0 0 0 0 1 1 0 CPU_D4
98 8 A TRI 0 0 0 0 1 1 0 CPU_D5
99 6 A TRI 0 0 0 0 1 1 0 CPU_D6
100 5 A TRI 0 0 0 0 1 1 0 CPU_D7
28 62 D OUTPUT 0 0 0 3 0 0 0 /CS10
29 61 D OUTPUT 0 0 0 3 0 0 0 /CS11
30 59 D OUTPUT 0 0 0 3 0 0 0 /CS12
31 57 D OUTPUT 0 0 0 3 0 0 0 /CS13
27 64 D OUTPUT s 0 0 0 1 15 1 0 /FIQ
85 128 H FF ! h 0 0 0 0 2 0 14 /IRQ1
50 80 E OUTPUT 0 0 0 2 1 0 0 RAM_A0
49 78 E OUTPUT 0 0 0 2 1 0 0 RAM_A1
48 77 E OUTPUT 0 0 0 2 1 0 0 RAM_A2
47 75 E OUTPUT 0 0 0 2 1 0 0 RAM_A3
46 73 E OUTPUT 0 0 0 2 1 0 0 RAM_A4
45 72 E OUTPUT 0 0 0 2 1 0 0 RAM_A5
44 70 E OUTPUT 0 0 0 2 1 0 0 RAM_A6
42 69 E OUTPUT 0 0 0 2 1 0 0 RAM_A7
41 67 E OUTPUT 0 0 0 2 1 0 0 RAM_A8
40 65 E OUTPUT 0 0 0 2 1 0 0 RAM_A9
37 49 D OUTPUT 0 0 0 2 1 0 0 RAM_A10
36 51 D OUTPUT 0 0 0 2 1 0 0 RAM_A11
35 53 D OUTPUT 0 0 0 2 1 0 0 RAM_A12
33 54 D OUTPUT 0 0 0 2 1 0 0 RAM_A13
32 56 D OUTPUT 0 0 0 0 0 0 0 RAM_A14
52 81 F TRI 0 0 0 3 1 1 0 RAM_D0
53 83 F TRI 0 0 0 3 1 1 0 RAM_D1
54 85 F TRI 0 0 0 3 1 1 0 RAM_D2
55 86 F TRI 0 0 0 3 1 1 0 RAM_D3
56 88 F TRI 0 0 0 3 1 1 0 RAM_D4
57 89 F TRI 0 0 0 3 1 1 0 RAM_D5
58 91 F TRI 0 0 0 3 1 1 0 RAM_D6
60 93 F TRI 0 0 0 3 1 1 0 RAM_D7
61 94 F OUTPUT 0 0 0 2 0 0 0 /RAM_RD
63 97 G OUTPUT 0 0 0 3 0 0 0 /RAM_WR
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 116 H TFFE 0 0 0 1 2 2 13 |COUNTER1:407|COUNT0
(84) 126 H TFFE 0 0 0 1 3 2 12 |COUNTER1:407|COUNT1
- 4 A TFFE 0 0 0 1 4 2 11 |COUNTER1:407|COUNT2
- 12 A TFFE 0 0 0 1 5 2 10 |COUNTER1:407|COUNT3
- 98 G TFFE 0 0 0 1 6 2 9 |COUNTER1:407|COUNT4
- 106 G TFFE 0 0 0 1 7 2 8 |COUNTER1:407|COUNT5
- 111 G TFFE 0 0 0 1 8 2 7 |COUNTER1:407|COUNT6
(67) 102 G TFFE 0 0 0 1 9 2 6 |COUNTER1:407|COUNT7
(8) 25 B TFFE 0 0 0 1 10 2 5 |COUNTER1:407|COUNT8
(14) 17 B TFFE 0 0 0 1 11 2 4 |COUNTER1:407|COUNT9
- 23 B TFFE 0 0 0 1 12 2 3 |COUNTER1:407|COUNT10
- 26 B TFFE 0 0 0 1 13 2 2 |COUNTER1:407|COUNT11
(10) 22 B TFFE 0 0 0 1 14 2 1 |COUNTER1:407|COUNT12
(7) 27 B TFFE 0 0 0 1 15 2 0 |COUNTER1:407|COUNT13
(13) 19 B SOFT s 0 0 0 2 0 0 0 CPU_D7~1
(65) 101 G SOFT s 0 0 0 2 0 0 0 RAM_D6~1
(16) 46 C SOFT 0 0 0 0 2 0 1 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node1
(24) 35 C SOFT 0 0 0 0 3 0 1 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node2
(21) 40 C SOFT 0 0 0 0 4 0 1 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node3
(22) 38 C SOFT 0 0 0 0 5 0 1 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node4
(20) 41 C SOFT 0 0 0 0 6 0 1 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node5
- 44 C SOFT 0 0 0 0 7 0 1 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node6
(15) 48 C SOFT 0 0 0 0 8 0 1 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node7
(25) 33 C TFFE 1 0 1 0 9 0 10 |TEST3:328|COUNTER:44|count7 (|TEST3:328|COUNTER:44|:4)
- 34 C DFFE 1 0 1 0 9 0 11 |TEST3:328|COUNTER:44|count6 (|TEST3:328|COUNTER:44|:5)
- 36 C DFFE 1 0 1 0 9 0 12 |TEST3:328|COUNTER:44|count5 (|TEST3:328|COUNTER:44|:6)
- 42 C DFFE 1 0 1 0 9 0 13 |TEST3:328|COUNTER:44|count4 (|TEST3:328|COUNTER:44|:7)
(19) 43 C DFFE 1 0 1 0 9 0 14 |TEST3:328|COUNTER:44|count3 (|TEST3:328|COUNTER:44|:8)
(17) 45 C DFFE 1 0 1 0 9 0 15 |TEST3:328|COUNTER:44|count2 (|TEST3:328|COUNTER:44|:9)
- 47 C DFFE 1 0 1 0 9 0 16 |TEST3:328|COUNTER:44|count1 (|TEST3:328|COUNTER:44|:10)
(23) 37 C DFFE 1 0 1 0 9 0 8 |TEST3:328|COUNTER:44|count0 (|TEST3:328|COUNTER:44|:11)
- 39 C TFFE 1 0 1 0 8 0 1 |TEST3:328|COUNTER:44|temp (|TEST3:328|COUNTER:44|:12)
- 122 H TFFE 0 0 0 0 4 0 1 |TEST3:328|:23
- 119 H TFFE 0 0 0 0 1 0 1 |TEST3:328|:26
(71) 109 G TFFE 0 0 0 0 1 0 1 |TEST3:328|:29
(81) 123 H TFFE 0 0 0 0 1 0 1 |TEST3:328|:32
- 100 G TFFE 0 0 0 0 1 0 9 |TEST3:328|:40
- 114 H DFFE 0 0 0 0 5 2 1 :281
(75) 113 H DFFE 0 0 0 0 5 2 0 :288
- 103 G DFFE 0 0 0 2 0 1 0 :353
(83) 125 H TFFE 0 0 0 0 5 1 5 |74161:276|p74161:sub|QD (|74161:276|p74161:sub|:6)
- 127 H TFFE 0 0 0 0 5 1 5 |74161:276|p74161:sub|QC (|74161:276|p74161:sub|:7)
(76) 115 H TFFE 0 0 0 0 2 1 5 |74161:276|p74161:sub|QB (|74161:276|p74161:sub|:8)
- 124 H TFFE 0 0 0 0 1 1 6 |74161:276|p74161:sub|QA (|74161:276|p74161:sub|:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------- LC4 |COUNTER1:407|COUNT2
| +----------------- LC12 |COUNTER1:407|COUNT3
| | +--------------- LC16 CPU_D0
| | | +------------- LC14 CPU_D1
| | | | +----------- LC13 CPU_D2
| | | | | +--------- LC11 CPU_D3
| | | | | | +------- LC9 CPU_D4
| | | | | | | +----- LC8 CPU_D5
| | | | | | | | +--- LC6 CPU_D6
| | | | | | | | | +- LC5 CPU_D7
| | | | | | | | | |
| | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC4 -> * * - - - - - - - - | * * - * * - * - | <-- |COUNTER1:407|COUNT2
Pin
75 -> * * - - - - - - - - | * * - - - - * * | <-- TCLK
LC117-> * * - - - - - - - - | * * - - - - * * | <-- CIS_SP
LC116-> * * - - - - - - - - | * * - * * - * * | <-- |COUNTER1:407|COUNT0
LC126-> * * - - - - - - - - | * * - * * - * - | <-- |COUNTER1:407|COUNT1
LC128-> * * - - - - - - - - | * * - - - - * * | <-- /IRQ1
LC81 -> - - * - - - - - - - | * - - - - - - - | <-- RAM_D0
LC83 -> - - - * - - - - - - | * - - - - - - - | <-- RAM_D1
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