LC85 -> - - - - * - - - - - | * - - - - - - - | <-- RAM_D2
LC86 -> - - - - - * - - - - | * - - - - - - - | <-- RAM_D3
LC88 -> - - - - - - * - - - | * - - - - - - - | <-- RAM_D4
LC89 -> - - - - - - - * - - | * - - - - - - - | <-- RAM_D5
LC91 -> - - - - - - - - * - | * - - - - - - - | <-- RAM_D6
LC93 -> - - - - - - - - - * | * - - - - - - - | <-- RAM_D7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                       Logic cells placed in LAB 'B'
        +------------- LC25 |COUNTER1:407|COUNT8
        | +----------- LC17 |COUNTER1:407|COUNT9
        | | +--------- LC23 |COUNTER1:407|COUNT10
        | | | +------- LC26 |COUNTER1:407|COUNT11
        | | | | +----- LC22 |COUNTER1:407|COUNT12
        | | | | | +--- LC27 |COUNTER1:407|COUNT13
        | | | | | | +- LC19 CPU_D7~1
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'B':
LC25 -> * * * * * * - | - * - * * - - - | <-- |COUNTER1:407|COUNT8
LC17 -> - * * * * * - | - * - * * - - - | <-- |COUNTER1:407|COUNT9
LC23 -> - - * * * * - | - * - * - - - - | <-- |COUNTER1:407|COUNT10
LC26 -> - - - * * * - | - * - * - - - - | <-- |COUNTER1:407|COUNT11
LC22 -> - - - - * * - | - * - * - - - - | <-- |COUNTER1:407|COUNT12

Pin
25   -> - - - - - - * | - * - * * * * - | <-- /CPU_CS2
22   -> - - - - - - * | - * - - - * - - | <-- /CPU_RD
75   -> * * * * * * - | * * - - - - * * | <-- TCLK
LC117-> * * * * * * - | * * - - - - * * | <-- CIS_SP
LC116-> * * * * * * - | * * - * * - * * | <-- |COUNTER1:407|COUNT0
LC126-> * * * * * * - | * * - * * - * - | <-- |COUNTER1:407|COUNT1
LC4  -> * * * * * * - | * * - * * - * - | <-- |COUNTER1:407|COUNT2
LC12 -> * * * * * * - | - * - * * - * - | <-- |COUNTER1:407|COUNT3
LC98 -> * * * * * * - | - * - * * - * - | <-- |COUNTER1:407|COUNT4
LC106-> * * * * * * - | - * - * * - * - | <-- |COUNTER1:407|COUNT5
LC111-> * * * * * * - | - * - * * - * - | <-- |COUNTER1:407|COUNT6
LC102-> * * * * * * - | - * - * * - - - | <-- |COUNTER1:407|COUNT7
LC128-> * * * * * * - | * * - - - - * * | <-- /IRQ1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC46 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node1
        | +----------------------------- LC35 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node2
        | | +--------------------------- LC40 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node3
        | | | +------------------------- LC38 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node4
        | | | | +----------------------- LC41 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node5
        | | | | | +--------------------- LC44 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node6
        | | | | | | +------------------- LC48 |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node7
        | | | | | | | +----------------- LC33 |TEST3:328|COUNTER:44|count7
        | | | | | | | | +--------------- LC34 |TEST3:328|COUNTER:44|count6
        | | | | | | | | | +------------- LC36 |TEST3:328|COUNTER:44|count5
        | | | | | | | | | | +----------- LC42 |TEST3:328|COUNTER:44|count4
        | | | | | | | | | | | +--------- LC43 |TEST3:328|COUNTER:44|count3
        | | | | | | | | | | | | +------- LC45 |TEST3:328|COUNTER:44|count2
        | | | | | | | | | | | | | +----- LC47 |TEST3:328|COUNTER:44|count1
        | | | | | | | | | | | | | | +--- LC37 |TEST3:328|COUNTER:44|count0
        | | | | | | | | | | | | | | | +- LC39 |TEST3:328|COUNTER:44|temp
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'C':
LC46 -> - - - - - - - - - - - - - * - - | - - * - - - - - | <-- |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node1
LC35 -> - - - - - - - - - - - - * - - - | - - * - - - - - | <-- |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node2
LC40 -> - - - - - - - - - - - * - - - - | - - * - - - - - | <-- |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node3
LC38 -> - - - - - - - - - - * - - - - - | - - * - - - - - | <-- |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node4
LC41 -> - - - - - - - - - * - - - - - - | - - * - - - - - | <-- |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node5
LC44 -> - - - - - - - - * - - - - - - - | - - * - - - - - | <-- |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node6
LC48 -> - - - - - - - * - - - - - - - - | - - * - - - - - | <-- |TEST3:328|COUNTER:44|LPM_ADD_SUB:157|addcore:adder|result_node7
LC33 -> - - - - - - * * * * * * * * * * | - - * - - - - - | <-- |TEST3:328|COUNTER:44|count7
LC34 -> - - - - - * * * * * * * * * * * | - - * - - - - - | <-- |TEST3:328|COUNTER:44|count6
LC36 -> - - - - * * * * * * * * * * * * | - - * - - - - - | <-- |TEST3:328|COUNTER:44|count5
LC42 -> - - - * * * * * * * * * * * * * | - - * - - - - - | <-- |TEST3:328|COUNTER:44|count4
LC43 -> - - * * * * * * * * * * * * * * | - - * - - - - - | <-- |TEST3:328|COUNTER:44|count3
LC45 -> - * * * * * * * * * * * * * * * | - - * - - - - - | <-- |TEST3:328|COUNTER:44|count2
LC47 -> * * * * * * * * * * * * * * * * | - - * - - - - - | <-- |TEST3:328|COUNTER:44|count1
LC37 -> * * * * * * * - - - - - - - * - | - - * - - - - - | <-- |TEST3:328|COUNTER:44|count0

Pin
LC100-> - - - - - - - * * * * * * * * * | - - * - - - - - | <-- |TEST3:328|:40


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                             Logic cells placed in LAB 'D'
        +------------------- LC62 /CS10
        | +----------------- LC61 /CS11
        | | +--------------- LC59 /CS12
        | | | +------------- LC57 /CS13
        | | | | +----------- LC64 /FIQ
        | | | | | +--------- LC49 RAM_A10
        | | | | | | +------- LC51 RAM_A11
        | | | | | | | +----- LC53 RAM_A12
        | | | | | | | | +--- LC54 RAM_A13
        | | | | | | | | | +- LC56 RAM_A14
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'D':
LC64 -> - - - - * - - - - - | - - - * - - - - | <-- /FIQ

Pin
14   -> - - - - - * - - - - | - - - * - - - - | <-- CPU_A10
16   -> - - - - - - * - - - | - - - * - - - - | <-- CPU_A11
17   -> - - - - - - - * - - | - - - * - - - - | <-- CPU_A12
19   -> - - - - - - - - * - | - - - * - - - - | <-- CPU_A13
20   -> * * * * - - - - - - | - - - * - - - - | <-- CPU_A19
21   -> * * * * - - - - - - | - - - * - - - - | <-- CPU_A20
24   -> * * * * - - - - - - | - - - * - - - - | <-- /CPU_CS1
25   -> - - - - - * * * * - | - * - * * * * - | <-- /CPU_CS2
83   -> - - - - * - - - - - | - - - * - - - - | <-- /TRIG-A
LC116-> - - - - * - - - - - | * * - * * - * * | <-- |COUNTER1:407|COUNT0
LC126-> - - - - * - - - - - | * * - * * - * - | <-- |COUNTER1:407|COUNT1
LC4  -> - - - - * - - - - - | * * - * * - * - | <-- |COUNTER1:407|COUNT2
LC12 -> - - - - * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT3
LC98 -> - - - - * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT4
LC106-> - - - - * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT5
LC111-> - - - - * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT6
LC102-> - - - - * - - - - - | - * - * * - - - | <-- |COUNTER1:407|COUNT7
LC25 -> - - - - * - - - - - | - * - * * - - - | <-- |COUNTER1:407|COUNT8
LC17 -> - - - - * - - - - - | - * - * * - - - | <-- |COUNTER1:407|COUNT9
LC23 -> - - - - * * - - - - | - * - * - - - - | <-- |COUNTER1:407|COUNT10
LC26 -> - - - - * - * - - - | - * - * - - - - | <-- |COUNTER1:407|COUNT11
LC22 -> - - - - * - - * - - | - * - * - - - - | <-- |COUNTER1:407|COUNT12
LC27 -> - - - - * - - - * - | - - - * - - - - | <-- |COUNTER1:407|COUNT13


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                             Logic cells placed in LAB 'E'
        +------------------- LC80 RAM_A0
        | +----------------- LC78 RAM_A1
        | | +--------------- LC77 RAM_A2
        | | | +------------- LC75 RAM_A3
        | | | | +----------- LC73 RAM_A4
        | | | | | +--------- LC72 RAM_A5
        | | | | | | +------- LC70 RAM_A6
        | | | | | | | +----- LC69 RAM_A7
        | | | | | | | | +--- LC67 RAM_A8
        | | | | | | | | | +- LC65 RAM_A9
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':

Pin
1    -> * - - - - - - - - - | - - - - * - - - | <-- CPU_A0
2    -> - * - - - - - - - - | - - - - * - - - | <-- CPU_A1
5    -> - - * - - - - - - - | - - - - * - - - | <-- CPU_A2
6    -> - - - * - - - - - - | - - - - * - - - | <-- CPU_A3
7    -> - - - - * - - - - - | - - - - * - - - | <-- CPU_A4
8    -> - - - - - * - - - - | - - - - * - - - | <-- CPU_A5
9    -> - - - - - - * - - - | - - - - * - - - | <-- CPU_A6
10   -> - - - - - - - * - - | - - - - * - - - | <-- CPU_A7
12   -> - - - - - - - - * - | - - - - * - - - | <-- CPU_A8
13   -> - - - - - - - - - * | - - - - * - - - | <-- CPU_A9
25   -> * * * * * * * * * * | - * - * * * * - | <-- /CPU_CS2
LC116-> * - - - - - - - - - | * * - * * - * * | <-- |COUNTER1:407|COUNT0
LC126-> - * - - - - - - - - | * * - * * - * - | <-- |COUNTER1:407|COUNT1
LC4  -> - - * - - - - - - - | * * - * * - * - | <-- |COUNTER1:407|COUNT2
LC12 -> - - - * - - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT3
LC98 -> - - - - * - - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT4
LC106-> - - - - - * - - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT5
LC111-> - - - - - - * - - - | - * - * * - * - | <-- |COUNTER1:407|COUNT6
LC102-> - - - - - - - * - - | - * - * * - - - | <-- |COUNTER1:407|COUNT7
LC25 -> - - - - - - - - * - | - * - * * - - - | <-- |COUNTER1:407|COUNT8
LC17 -> - - - - - - - - - * | - * - * * - - - | <-- |COUNTER1:407|COUNT9


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                           Logic cells placed in LAB 'F'
        +----------------- LC81 RAM_D0
        | +--------------- LC83 RAM_D1
        | | +------------- LC85 RAM_D2
        | | | +----------- LC86 RAM_D3
        | | | | +--------- LC88 RAM_D4
        | | | | | +------- LC89 RAM_D5
        | | | | | | +----- LC91 RAM_D6
        | | | | | | | +--- LC93 RAM_D7
        | | | | | | | | +- LC94 /RAM_RD
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':

Pin
64   -> * - - - - - - - - | - - - - - * - - | <-- CMOS_D0
65   -> - * - - - - - - - | - - - - - * - - | <-- CMOS_D1
67   -> - - * - - - - - - | - - - - - * - - | <-- CMOS_D2
68   -> - - - * - - - - - | - - - - - * - - | <-- CMOS_D3
69   -> - - - - * - - - - | - - - - - * - - | <-- CMOS_D4
70   -> - - - - - * - - - | - - - - - * - - | <-- CMOS_D5
71   -> - - - - - - * - - | - - - - - * - - | <-- CMOS_D6
72   -> - - - - - - - * - | - - - - - * - - | <-- CMOS_D7
25   -> * * * * * * * * * | - * - * * * * - | <-- /CPU_CS2
22   -> - - - - - - - - * | - * - - - * - - | <-- /CPU_RD
23   -> * * * * * * * * - | - - - - - * * - | <-- /CPU_WR
LC16 -> * - - - - - - - - | - - - - - * - - | <-- CPU_D0
LC14 -> - * - - - - - - - | - - - - - * - - | <-- CPU_D1
LC13 -> - - * - - - - - - | - - - - - * - - | <-- CPU_D2
LC11 -> - - - * - - - - - | - - - - - * - - | <-- CPU_D3
LC9  -> - - - - * - - - - | - - - - - * - - | <-- CPU_D4
LC8  -> - - - - - * - - - | - - - - - * - - | <-- CPU_D5
LC6  -> - - - - - - * - - | - - - - - * - - | <-- CPU_D6
LC5  -> - - - - - - - * - | - - - - - * - - | <-- CPU_D7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:           c:\max2work\work\cis_cpld6\cis_cpld.rpt
cis_cpld

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':