library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity and1 is
port(A: in std_logic_vector(2 downto 0);
     B: in std_logic_vector(2 downto 0);
     D: out std_logic_vector(5 downto 0));
end and1;
architecture rt2 of and1 is
signal aa,bb,cc:std_logic_vector(4 downto 0);
begin
     process(A,B)
     begin
     if (B(0)='1') then
          aa<="00" & A;
     elsif (B(0)='0') then
           aa<="00000";
     end if;
     if (B(1)='1') then
          bb<='0' & A & '0';
     elsif (B(1)='0') then
           bb<="00000";
     end if;
     if (B(2)='1') then
          cc<=A & "00";
     elsif (B(2)='0') then
           cc<="00000";
     end if;
     D<=aa + bb + cc;
     end process;
end rt2;