?? s12_pim.h
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/*****************************************************************************/
/* COPYRIGHT (c) MOTOROLA 2002 */
/* */
/* File Name : $RCSfile: s12_pim.h,v $ */
/* */
/* Current Revision : $Revision: 1.2 $ */
/* */
/* PURPOSE: header file for HCS12 PIM block */
/* */
/* *********************************************************************** */
/* * THIS CODE IS ONLY INTENDED AS AN EXAMPLE OF CODE FOR THE * */
/* * METROWERKS COMPILER AND THE STAR12 EVB AND HAS ONLY BEEN GIVEN A * */
/* * MIMIMUM LEVEL OF TEST. IT IS PROVIDED 'AS SEEN' WITH NO GUARANTEES * */
/* * AND NO PROMISE OF SUPPORT. * */
/* *********************************************************************** */
/* */
/* DESCRIPTION: Defines the i/o port integration module (PIM) block as a */
/* datastructure of type tPIM. */
/* */
/* PIM Datastructure base address (out of reset) - */
/* */
/* S12DP256 : 0x0240 */
/* */
/* The datastructure compiled can be determined by the #define's S12DP256, */
/* S12xxx, etc. These definitions can be found in "s12_common.h". */
/* The MCU id can be #defined in a "target.h" header file or included as a */
/* complier command line argument as -DS12DP256. */
/* Currently only S12DP256 is supported. */
/* */
/* Multiple register descriptions are used when a differing bit structure */
/* exists between parts. In the case of additional bit definitions within */
/* the same register, then only the full register description is used. */
/* */
/* */
/* AUTHOR: r32151 LOCATION: SPSEKB LAST EDIT DATE: 14/03/02 */
/* */
/* UPDATE HISTORY */
/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
/* --- ------ -------- --------------------- */
/* 1.00 r32151 01/05/00 - */
/* 1.01 r32151 10/05/00 - Added some bits detail to partid comments. */
/* - corrected reduced drive union names uRDHP */
/* to uRDRH & uRDJP -> uRDRJ */
/* - Changed #include <s12_common.h> */
/* to #include "s12_common.h" */
/* 1.02 r32151 25/05/00 - Corrected declarations of rsvt, rsvs & rsvm*/
/* 1.03 r32151 26/07/01 - UPDATED TO SUPPORT MASK 0K79X */
/* - changed CPU id MCSDP256 to S12DP256 */
/* - Added new MODRR module routing register at */
/* location (offset 0x0017) - prev reserved */
/* - Added disclaimer and reformated file info. */
/* 1.1 r32151 11/03/02 - cleaned up file info */
/* - Modified revision numbering to match RCS */
/* 1.2 r32151 14/03/02 - made all registers volatile */
/* 2.0 r58711 17/09/02 - added support for C32 */
/* */
/*===========================================================================*/
/* Motorola reserves the right to make changes without further notice to any */
/* product herein to improve reliability, function, or design. Motorola does */
/* not assume any liability arising out of the application or use of any */
/* product, circuit, or software described herein; neither does it convey */
/* any license under its patent rights nor the rights of others. Motorola */
/* products are not designed, intended, or authorized for use as components */
/* in systems intended for surgical implant into the body, or other */
/* applications intended to support life, or for any other application in */
/* which the failure of the Motorola product could create a situation where */
/* personal injury or death may occur. Should Buyer purchase or use Motorola */
/* products for any such intended or unauthorized application, Buyer shall */
/* indemnify and hold Motorola and its officers, employees, subsidiaries, */
/* affiliates, and distributors harmless against all claims costs, damages, */
/* and expenses, and reasonable attorney fees arising out of, directly or */
/* indirectly, any claim of personal injury or death associated with such */
/* unintended or unauthorized use, even if such claim alleges that Motorola */
/* was negligent regarding the design or manufacture of the part. Motorola */
/* and the Motorola logo* are registered trademarks of Motorola Ltd. */
/*****************************************************************************/
#ifndef S12_PIM_H /*prevent duplicated includes */
#define S12_PIM_H
#ifndef S12_COMMON_H /*prevent duplicated includes */
#include "s12_common.h"
#endif
/****************************** PORT T *************************/
typedef union uPTT /*i/o register */
{
tU08 byte;
struct
{
tU08 ptt0 :1; /*i/o port pins */
tU08 ptt1 :1;
tU08 ptt2 :1;
tU08 ptt3 :1;
tU08 ptt4 :1;
tU08 ptt5 :1;
tU08 ptt6 :1;
tU08 ptt7 :1;
}bit;
}tPTT;
#define PTT0 0x01 /*bit masks */
#define PTT1 0x02
#define PTT2 0x04
#define PTT3 0x08
#define PTT4 0x10
#define PTT5 0x20
#define PTT6 0x40
#define PTT7 0x80
typedef union uPTIT /*input register */
{
tU08 byte;
struct
{
tU08 ptit0 :1; /*i/o port pins */
tU08 ptit1 :1;
tU08 ptit2 :1;
tU08 ptit3 :1;
tU08 ptit4 :1;
tU08 ptit5 :1;
tU08 ptit6 :1;
tU08 ptit7 :1;
}bit;
}tPTIT;
#define PTIT0 0x01 /*bit masks */
#define PTIT1 0x02
#define PTIT2 0x04
#define PTIT3 0x08
#define PTIT4 0x10
#define PTIT5 0x20
#define PTIT6 0x40
#define PTIT7 0x80
typedef union uDDRT /*data direction register */
{
tU08 byte;
struct
{
tU08 ddrt0 :1; /*data direction bits (0:input;1:output) */
tU08 ddrt1 :1;
tU08 ddrt2 :1;
tU08 ddrt3 :1;
tU08 ddrt4 :1;
tU08 ddrt5 :1;
tU08 ddrt6 :1;
tU08 ddrt7 :1;
}bit;
}tDDRT;
#define DDRT0 0x01 /*bit masks */
#define DDRT1 0x02
#define DDRT2 0x04
#define DDRT3 0x08
#define DDRT4 0x10
#define DDRT5 0x20
#define DDRT6 0x40
#define DDRT7 0x80
typedef union uRDRT /*reduced drive register */
{
tU08 byte;
struct
{
tU08 rdrt0 :1; /*reduced drive bits (0:full;1:reduced) */
tU08 rdrt1 :1;
tU08 rdrt2 :1;
tU08 rdrt3 :1;
tU08 rdrt4 :1;
tU08 rdrt5 :1;
tU08 rdrt6 :1;
tU08 rdrt7 :1;
}bit;
}tRDRT;
#define RDRT0 0x01 /*bit masks */
#define RDRT1 0x02
#define RDRT2 0x04
#define RDRT3 0x08
#define RDRT4 0x10
#define RDRT5 0x20
#define RDRT6 0x40
#define RDRT7 0x80
typedef union uPERT /*pull-up/dn enable register */
{
tU08 byte;
struct
{
tU08 pert0 :1; /*pull-up/dn bits (1:enabled) */
tU08 pert1 :1;
tU08 pert2 :1;
tU08 pert3 :1;
tU08 pert4 :1;
tU08 pert5 :1;
tU08 pert6 :1;
tU08 pert7 :1;
}bit;
}tPERT;
#define PERT0 0x01 /*bit masks */
#define PERT1 0x02
#define PERT2 0x04
#define PERT3 0x08
#define PERT4 0x10
#define PERT5 0x20
#define PERT6 0x40
#define PERT7 0x80
typedef union uPPST /*pull-up/dn polarity register */
{
tU08 byte;
struct
{
tU08 ppst0 :1; /*pull-up/dn bits (0:pull-up;1:pull-dn) */
tU08 ppst1 :1;
tU08 ppst2 :1;
tU08 ppst3 :1;
tU08 ppst4 :1;
tU08 ppst5 :1;
tU08 ppst6 :1;
tU08 ppst7 :1;
}bit;
}tPPST;
#define PPST0 0x01 /*bit masks */
#define PPST1 0x02
#define PPST2 0x04
#define PPST3 0x08
#define PPST4 0x10
#define PPST5 0x20
#define PPST6 0x40
#define PPST7 0x80
/****************************** PORT S **************************/
typedef union uPTS /*i/o register */
{
tU08 byte;
struct
{
tU08 pts0 :1; /*i/o port pins */
tU08 pts1 :1;
tU08 pts2 :1;
tU08 pts3 :1;
tU08 pts4 :1;
tU08 pts5 :1;
tU08 pts6 :1;
tU08 pts7 :1;
}bit;
}tPTS;
#define PTS0 0x01 /*bit masks */
#define PTS1 0x02
#define PTS2 0x04
#define PTS3 0x08
#define PTS4 0x10
#define PTS5 0x20
#define PTS6 0x40
#define PTS7 0x80
typedef union uPTIS /*input register */
{
tU08 byte;
struct
{
tU08 ptis0 :1; /*i/o port pins */
tU08 ptis1 :1;
tU08 ptis2 :1;
tU08 ptis3 :1;
tU08 ptis4 :1;
tU08 ptis5 :1;
tU08 ptis6 :1;
tU08 ptis7 :1;
}bit;
}tPTIS;
#define PTIS0 0x01 /*bit masks */
#define PTIS1 0x02
#define PTIS2 0x04
#define PTIS3 0x08
#define PTIS4 0x10
#define PTIS5 0x20
#define PTIS6 0x40
#define PTIS7 0x80
typedef union uDDRS /*data direction register */
{
tU08 byte;
struct
{
tU08 ddrs0 :1; /*data direction bits (0:input;1:output) */
tU08 ddrs1 :1;
tU08 ddrs2 :1;
tU08 ddrs3 :1;
tU08 ddrs4 :1;
tU08 ddrs5 :1;
tU08 ddrs6 :1;
tU08 ddrs7 :1;
}bit;
}tDDRS;
#define DDRS0 0x01 /*bit masks */
#define DDRS1 0x02
#define DDRS2 0x04
#define DDRS3 0x08
#define DDRS4 0x10
#define DDRS5 0x20
#define DDRS6 0x40
#define DDRS7 0x80
typedef union uRDRS /*reduced drive register */
{
tU08 byte;
struct
{
tU08 rdrs0 :1; /*reduced drive bits (0:full;1:reduced) */
tU08 rdrs1 :1;
tU08 rdrs2 :1;
tU08 rdrs3 :1;
tU08 rdrs4 :1;
tU08 rdrs5 :1;
tU08 rdrs6 :1;
tU08 rdrs7 :1;
}bit;
}tRDRS;
#define RDRS0 0x01 /*bit masks */
#define RDRS1 0x02
#define RDRS2 0x04
#define RDRS3 0x08
#define RDRS4 0x10
#define RDRS5 0x20
#define RDRS6 0x40
#define RDRS7 0x80
typedef union uPERS /*pull-up/dn enable register */
{
tU08 byte;
struct
{
tU08 pers0 :1; /*pull-up/dn bits (1:enabled) */
tU08 pers1 :1;
tU08 pers2 :1;
tU08 pers3 :1;
tU08 pers4 :1;
tU08 pers5 :1;
tU08 pers6 :1;
tU08 pers7 :1;
}bit;
}tPERS;
#define PERS0 0x01 /*bit masks */
#define PERS1 0x02
#define PERS2 0x04
#define PERS3 0x08
#define PERS4 0x10
#define PERS5 0x20
#define PERS6 0x40
#define PERS7 0x80
typedef union uPPSS /*pull-up/dn polarity register */
{
tU08 byte;
struct
{
tU08 ppss0 :1; /*pull-up/dn bits (0:pull-up;1:pull-dn) */
tU08 ppss1 :1;
tU08 ppss2 :1;
tU08 ppss3 :1;
tU08 ppss4 :1;
tU08 ppss5 :1;
tU08 ppss6 :1;
tU08 ppss7 :1;
}bit;
}tPPSS;
#define PPSS0 0x01 /*bit masks */
#define PPSS1 0x02
#define PPSS2 0x04
#define PPSS3 0x08
#define PPSS4 0x10
#define PPSS5 0x20
#define PPSS6 0x40
#define PPSS7 0x80
typedef union uWOMS /*wired-or mode register */
{
tU08 byte;
struct
{
tU08 woms0 :1; /*wired-or bits (1:enabled) */
tU08 woms1 :1;
tU08 woms2 :1;
tU08 woms3 :1;
tU08 woms4 :1;
tU08 woms5 :1;
tU08 woms6 :1;
tU08 woms7 :1;
}bit;
}tWOMS;
#define WOMS0 0x01 /*bit masks */
#define WOMS1 0x02
#define WOMS2 0x04
#define WOMS3 0x08
#define WOMS4 0x10
#define WOMS5 0x20
#define WOMS6 0x40
#define WOMS7 0x80
/****************************** PORT M **************************/
typedef union uPTM /*i/o register */
{
tU08 byte;
struct
{
tU08 ptm0 :1; /*i/o port pins */
tU08 ptm1 :1;
tU08 ptm2 :1;
tU08 ptm3 :1;
tU08 ptm4 :1;
tU08 ptm5 :1;
tU08 ptm6 :1;
tU08 ptm7 :1;
}bit;
}tPTM;
#define PTM0 0x01 /*bit masks */
#define PTM1 0x02
#define PTM2 0x04
#define PTM3 0x08
#define PTM4 0x10
#define PTM5 0x20
#define PTM6 0x40
#define PTM7 0x80
typedef union uPTIM /*input register */
{
tU08 byte;
struct
{
tU08 ptim0 :1; /*i/o port pins */
tU08 ptim1 :1;
tU08 ptim2 :1;
tU08 ptim3 :1;
tU08 ptim4 :1;
tU08 ptim5 :1;
tU08 ptim6 :1;
tU08 ptim7 :1;
}bit;
}tPTIM;
#define PTIM0 0x01 /*bit masks */
#define PTIM1 0x02
#define PTIM2 0x04
#define PTIM3 0x08
#define PTIM4 0x10
#define PTIM5 0x20
#define PTIM6 0x40
#define PTIM7 0x80
typedef union uDDRM /*data direction register */
{
tU08 byte;
struct
{
tU08 ddrm0 :1; /*data direction bits (0:input;1:output) */
tU08 ddrm1 :1;
tU08 ddrm2 :1;
tU08 ddrm3 :1;
tU08 ddrm4 :1;
tU08 ddrm5 :1;
tU08 ddrm6 :1;
tU08 ddrm7 :1;
}bit;
}tDDRM;
#define DDRM0 0x01 /*bit masks */
#define DDRM1 0x02
#define DDRM2 0x04
#define DDRM3 0x08
#define DDRM4 0x10
#define DDRM5 0x20
#define DDRM6 0x40
#define DDRM7 0x80
typedef union uRDRM /*reduced drive register */
{
tU08 byte;
struct
{
tU08 rdrm0 :1; /*reduced drive bits (0:full;1:reduced) */
tU08 rdrm1 :1;
tU08 rdrm2 :1;
tU08 rdrm3 :1;
tU08 rdrm4 :1;
tU08 rdrm5 :1;
tU08 rdrm6 :1;
tU08 rdrm7 :1;
}bit;
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