;------------------------------------------------------------------------------
;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source          : cstartup.s
;- Object               : Generic CStartup
;- Compilation flag     : None
;-
;- 1.0 20/Nov/03 JPP    : Creation ARM ADS and Interrupt out SVC mode check IRQ
;------------------------------------------------------------------------------
;--------------------------------
;- ARM Core Mode and Status Bits
;--------------------------------

STACK_TOP_MEMORY        EQU     0x00218000

ARM_MODE_FIQ            EQU     0x11
ARM_MODE_IRQ            EQU     0x12
ARM_MODE_SVC            EQU     0x13
ARM_MODE_ABORT          EQU     0x17
ARM_MODE_UNDEF          EQU     0x1B
ARM_MODE_SYS            EQU     0x1F

I_BIT                   EQU     0x80
F_BIT                   EQU     0x40

;------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.
;------------------------------------------------------------------------------
                AREA        reset, CODE, READONLY


;	IMPORT __use_no_semihosting_swi
;------------------------------------------------------------------------------
;- Define the entry point
;------------------------

	EXPORT	__ENTRY
__ENTRY
	IMPORT	      AT91F_DataAbort
        IMPORT        AT91F_Undef         ; 0x04 Undefined Instruction
        IMPORT        AT91F_Software    	; 0x08 Software Interrupt
        IMPORT        AT91F_FetchAbort  	; 0x0c Prefetch Abort
        IMPORT        AT91F_DataAbort    	; 0x10 Data Abort

;------------------------------------------------------------------------------
;- Exception vectors ( before Remap )
;------------------------------------
;- These vectors are read at address 0.
;- They absolutely requires to be in relative addresssing mode in order to 
;- guarantee a valid jump. For the moment, all are just looping (what may be 
;- dangerous in a final system). If an exception occurs before remap, this 
;- would result in an infinite loop. 
;------------------------------------------------------------------------------
                B           InitReset       	; reset
undefvec
                B           AT91F_Undef         ; 0x04 Undefined Instruction
swivec
                B           AT91F_Software    	; 0x08 Software Interrupt
pabtvec
                B           AT91F_FetchAbort  	; 0x0c Prefetch Abort
dabtvec
                B           AT91F_DataAbort    	; 0x10 Data Abort
rsvdvec
                B           rsvdvec         	; 0x14 reserved
irqvec
                ldr         pc, [pc,#-0xF20]    ; 0x18 IRQ : read the AIC
fiqvec
                ldr         pc, [pc,#-0xF20]   	; 0x1c FIQ

;-------------------
;- The reset handler
;-------------------
InitReset

;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ_ENTRY/IRQ_EXIT macro are used.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt not requires stack If in your application it required you must
;- be define here.
;- Other stacks are defined by default to save one word each.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;- User stack size is not defined and is limited by the free external SRAM.
;------------------------------------------------------------------------------

;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------
;- The processor will remain in the last initialized mode.
;------------------------------------------------------------------------------
IRQ_STACK_SIZE      	EQU     (2*8*4)     ; 2 words per interrupt priority level
ABT_STACK_SIZE      	EQU     (3*4)       ; 3 word
UND_STACK_SIZE          EQU     (3*4)       ; 3 word



;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------

;- get the top of memory
                ldr     r0, =STACK_TOP_MEMORY

;- Set up Interrupt Mode and set IRQ Mode Stack
                msr     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack IRQ
                sub     r0, r0, #IRQ_STACK_SIZE

;- Set up Abort Mode and set Abort Mode Stack
                msr     CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack Abort
                sub     r0, r0, #ABT_STACK_SIZE

;- Set up Undefined Instruction Mode and set Undef Mode Stack
                msr     CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT
                mov     r13, r0                     ; Init stack Undef
                sub     r0, r0, #UND_STACK_SIZE

;- Set up user Mode and set System Mode Stack
                msr     CPSR_c, #ARM_MODE_SVC | F_BIT
                bic     r0, r0, #3                  ; Insure word alignement
               	mov     sp, r0                      ; Init stack System

;------------------------------------------------------------------------------
;- Low level Init is performed in a C function: AT91F_LowLevelInit (APMC, AIC, EBI, ....)
;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
;----------------------------------------------------------------------

	IMPORT     AT91F_LowLevelInit

	ldr       r0, = AT91F_LowLevelInit
	mov       lr, pc
	bx        r0

;------------------------------------------------------------------------------
;- Initialise C variables
;------------------------
;- Following labels are automatically generated by the linker. 
;- RO: Read-only = the code
;- RW: Read Write = the data pre-initialized and zero-initialized.
;- ZI: Zero-Initialized.
;- Pre-initialization values are located after the code area in the image.
;- Zero-initialized datas are mapped after the pre-initialized.
;- Note on the Data position : 
;- If using the ARMSDT, when no -rw-base option is used for the linker, the 
;- data area is mapped after the code. You can map the data either in internal
;- SRAM ( -rw-base=0x40 or 0x34) or in external SRAM ( -rw-base=0x2000000 ).
;- Note also that to improve the code density, the pre_initialized data must 
;- be limited to a minimum.
;------------------------------------------------------------------------------

	add     r2, pc,#-(8+.-CInitData)  ; @ where to read values (relative)
	ldmia   r2, {r0, r1, r3, r4}
	
	cmp         r0, r1                  ; Check that they are different
	beq         EndRW
LoopRW	
	cmp         r1, r3                  ; Copy init data
	ldrcc       r2, [r0], #4
	strcc       r2, [r1], #4
	bcc         LoopRW
EndRW

	mov         r2, #0
LoopZI	
	cmp         r3, r4                  ; Zero init
	strcc       r2, [r3], #4
	bcc         LoopZI
 
	b           EndInitC
                
CInitData
 	IMPORT      |Image$$RO$$Limit|      ; End of ROM code (=start of ROM data)
	IMPORT      |Image$$RW$$Base|       ; Base of RAM to initialise
	IMPORT      |Image$$ZI$$Base|       ; Base and limit of area
	IMPORT      |Image$$ZI$$Limit|      ; Top of zero init segment
	
	DCD     |Image$$RO$$Limit|      ; End of ROM code (=start of ROM data)
 	DCD     |Image$$RW$$Base|       ; Base of RAM to initialise
 	DCD     |Image$$ZI$$Base|       ; Base and limit of area
 	DCD     |Image$$ZI$$Limit|      ; Top of zero init segment
EndInitC

  
;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;- Branch must be performed by an interworking call as either an ARM or Thumb 
;- main C function must be supported. This makes the code not position-
;- independant. A Branch with link would generate errors 
;------------------------------------------------------------------------------
	IMPORT      main
_main
__main
	EXPORT    _main
	EXPORT    __main
	ldr       r0, =main
	mov       lr, pc
	bx        r0

;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
End
	b           End
	
	
	
            END