?? project.frp
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******************************************************************************************
PSDsoft Express Version 8.40
Output of PSD Fitter
******************************************************************************************
PROJECT : project DATE : 03/21/2005
DEVICE : uPSD3434E TIME : 21:51:34
FIT OPTION : Keep Current
DESCRIPTION: DK3400 USB demo
******************************************************************************************
==== Pin Layout for U (80-Pin TQFP) Package Type ====
-----------------------------
| |
|1 ] pd2 adio4 [41| Address Bus a4/Data Port d4, ad4
|2 ] p3_3 p3_5 [42|
RED_LED |3 ] pd1 adio5 [43| Address Bus a5/Data Port d5, ad5
ale |4 ] pd0 p3_6 [44|
|5 ] pc7 adio6 [45| Address Bus a6/Data Port d6, ad6
tdo, TDO |6 ] pc6/TDO p3_7 [46|
tdi, TDI |7 ] pc5/TDI adio7 [47| Address Bus a7/Data Port d7, ad7
JTAG_debug_pin |8 ] debug Xtal1 [48| Xtal1
|9 ] pc4/TERR Xtal2 [49| Xtal2
|10] 3.3V VCC 5.0V VCC [50|
USB_plus |11] USBp N/C [51|
|12] 5.0V VCC p1_0 [52|
|13] GND N/C [53|
USB_minus |14] USBm p1_1 [54|
|15] pc3/TSTAT N/C [55|
|16] pc2 p1_2 [56|
tck, TCK |17] pc1/TCK N/C [57|
|18] p4_7 p1_3 [58|
|19] p4_6 p1_4 [59|
tms, TMS |20] pc0/TMS p1_5 [60|
|21] pa7 p1_6 [61|
|22] pa6 cntl0 [62| _wr
|23] p4_5 cntl2 [63| _psen
|24] pa5 p1_7 [64|
|25] p4_4 cntl1 [65| _rd
|26] pa4 pb7 [66|
|27] p4_3 pb6 [67|
|28] pa3 Reset_In [68| _Reset_In
|29] GND GND [69|
|30] p4_2 Vref [70| VREF
|31] p4_1 pb5 [71|
|32] pa2 AVcc [72|
|33] p4_0 pb4 [73|
|34] pa1 pb3 [74|
|35] pa0 p3_0 [75|
ad0, Address Bus a0/Data Port d0 |36] adio0 pb2 [76|
ad1, Address Bus a1/Data Port d1 |37] adio1 p3_1 [77|
ad2, Address Bus a2/Data Port d2 |38] adio2 pb1 [78|
ad3, Address Bus a3/Data Port d3 |39] adio3 p3_2 [79|
|40] p3_4 pb0 [80|
| |
-----------------------------
==== Global Configuration ====
Data Bus : 8-Bit
Address/Data Mode : Multiplexed
ALE/AS Signal : Active High
Control Signals : /WR, /RD, /PSEN
Main PSD flash memory will reside in this space at power-up : Data space
Secondary PSD flash memory will reside in this space at power-up : Both Program and Data space
Enable Chip-Select Input(/CSI) : OFF
Standby Voltage Input (PC2) : OFF
Standby-on Indicator (PC4) : OFF
RDY/Busy function (PC3) : OFF
Load Micro-Cell on : edge
Security Protection : OFF
==== DataBus_IMC access information ====
CSIOP
Location Address Offset Register Name Signals
--------------------------------------------------------
===== Resource Usage Summary =====
Total Product Terms Used: 15
Device Resources used / total
------------------------------------------------
Port A: (pins 35 34 32 28 26 24 22 21)
I/O Pins : 0 / 8
GP I/O or Address Out : 0
Peripheral I/O : 0
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
Combinatorial Outputs : 0
Registered Outputs : 0
Other Information
Microcells : 0 / 8
Micro-Cells AB :
Buried Microcells : 0
Output Microcells : 0
Product Terms : 0 / 24
Control Product Terms : 0 / 34
Port B: (pins 80 78 76 74 73 71 67 66)
I/O Pins : 0 / 8
GP I/O or Address Out : 0
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
Combinatorial Outputs : 0
Registered Outputs : 0
Other Information
Microcells : 0 / 8
Micro-Cells AB :
Buried Microcells : 0
Output Microcells : 0
Micro-Cells BC :
Buried Microcells : 0
Output Microcells : 0
Product Terms : 0 / 24
Control Product Terms : 0 / 34
Port C: (pins 20 17 16 15 9 7 6 5)
I/O Pins : 4 / 8
GP I/O or Address Out : 0
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
JTAG signals : 4
Standby Voltage Input : 0
Rdy/Bsy signal : 0
Standby On Indicator : 0
Combinatorial Outputs : 0
Registered Outputs : 0
Other Information
Microcells : 0 / 8
Micro-Cells BC :
Buried Microcells : 0
Output Microcells : 0
Product Terms : 0 / 32
Control Product Terms : 0 / 34
Port D: (pins 4 3 1)
I/O Pins : 2 / 3
GP I/O or Address Out : 1
Logic Inputs : 0
Chip-Select Input : 0
Clock Input : 0
Control Signal Input : 1
Fast Decoding Outputs : 0
Other Information
Product Terms : 0 / 3
Control Product Terms : 0 / 3
==== OMC Resource Assignment ====
Resources PT User
Used Allocation Name
---------------------------------------------------------
Micro-Cell AB :
Micro-Cell BC :
External Chip Select :
========= Equations =========
DPLD EQUATIONS :
=======================
fs0 = !pdn & !pgr3 & !pgr2 & !pgr1 & pgr0 & a15;
fs1 = !pdn & !pgr3 & !pgr2 & pgr1 & !pgr0 & a15;
fs2 = !pdn & !pgr3 & !pgr2 & pgr1 & pgr0 & a15;
fs3 = !pdn & !pgr3 & pgr2 & !pgr1 & !pgr0 & a15;
fs4 = !pdn & !pgr3 & pgr2 & !pgr1 & pgr0 & a15;
fs5 = !pdn & !pgr3 & pgr2 & pgr1 & !pgr0 & a15;
fs6 = !pdn & !pgr3 & pgr2 & pgr1 & pgr0 & a15;
fs7 = !pdn & pgr3 & !pgr2 & !pgr1 & !pgr0 & a15;
csboot0 = !pdn & !a15 & !a14 & !a13;
csboot1 = !pdn & !pgr3 & !pgr2 & !pgr1 & !pgr0 & a15 & !a14 & a13;
csboot2 = !pdn & !pgr3 & !pgr2 & !pgr1 & !pgr0 & a15 & a14 & !a13;
csboot3 = !pdn & !pgr3 & !pgr2 & !pgr1 & !pgr0 & a15 & a14 & a13;
csiop = !pdn & !a15 & a14 & a13 & a12 & a11 & a10 & a9 & a8;
rs0 = !pdn & !pgr3 & !pgr2 & !pgr1 & !pgr0 & a15 & !a14 & !a13;
jtagsel = !_reset;
PORTA EQUATIONS :
=======================
PORTB EQUATIONS :
=======================
PORTC EQUATIONS :
=======================
PORTD EQUATIONS :
=======================
--- End ---
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