--*******************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*******************************
ENTITY ch6_1_1 IS
  PORT(
       CP,D:IN STD_LOGIC;
       Q   :OUT STD_LOGIC
       );
END ch6_1_1;
--********************************
ARCHITECTURE a OF ch6_1_1 IS
BEGIN
  PROCESS(CP)
    BEGIN
      IF CP'event AND CP='1'THEN
          Q<=D;
      END IF;
  END PROCESS;
END a;