?? rs觸發器.txt
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch6_1_3 is port( s,r :in std_logic;
q,not_q :out std_logic);
end ch6_1_3;
architecture a of ch6_1_3 is
signal qn,not_qn: std_logic;
begin
qn<=r nor not_qn;
not_qn<=s nor qn;
q<=qn;
not_q<=not_qn;
end a;
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