r = Fitter-inserted logic cell


Device-Specific Information:                 c:\documents and settings\reg.rpt
reg

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC24 dout0
        | +------------- LC25 dout1
        | | +----------- LC22 dout2
        | | | +--------- LC23 dout3
        | | | | +------- LC21 dout4
        | | | | | +----- LC20 dout5
        | | | | | | +--- LC19 dout6
        | | | | | | | +- LC17 dout7
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC24 -> * - - - - - - - | - * | <-- dout0
LC25 -> - * - - - - - - | - * | <-- dout1
LC22 -> - - * - - - - - | - * | <-- dout2
LC23 -> - - - * - - - - | - * | <-- dout3
LC21 -> - - - - * - - - | - * | <-- dout4
LC20 -> - - - - - * - - | - * | <-- dout5
LC19 -> - - - - - - * - | - * | <-- dout6
LC17 -> - - - - - - - * | - * | <-- dout7

Pin
43   -> - - - - - - - - | - - | <-- clk
13   -> * - - - - - - - | - * | <-- din0
14   -> - * - - - - - - | - * | <-- din1
12   -> - - * - - - - - | - * | <-- din2
11   -> - - - * - - - - | - * | <-- din3
9    -> - - - - * - - - | - * | <-- din4
8    -> - - - - - * - - | - * | <-- din5
7    -> - - - - - - * - | - * | <-- din6
6    -> - - - - - - - * | - * | <-- din7
4    -> * * * * * * * * | - * | <-- load
5    -> * * * * * * * * | - * | <-- reset


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                 c:\documents and settings\reg.rpt
reg

** EQUATIONS **

clk      : INPUT;
din0     : INPUT;
din1     : INPUT;
din2     : INPUT;
din3     : INPUT;
din4     : INPUT;
din5     : INPUT;
din6     : INPUT;
din7     : INPUT;
load     : INPUT;
reset    : INPUT;

-- Node name is 'dout0' = 'p_state0' 
-- Equation name is 'dout0', location is LC024, type is output.
 dout0   = DFFE( _EQ001 $  GND, GLOBAL( clk),  VCC,  reset,  VCC);
  _EQ001 =  din0 &  load
         #  dout0 & !load;

-- Node name is 'dout1' = 'p_state1' 
-- Equation name is 'dout1', location is LC025, type is output.
 dout1   = DFFE( _EQ002 $  GND, GLOBAL( clk),  VCC,  reset,  VCC);
  _EQ002 =  din1 &  load
         #  dout1 & !load;

-- Node name is 'dout2' = 'p_state2' 
-- Equation name is 'dout2', location is LC022, type is output.
 dout2   = DFFE( _EQ003 $  GND, GLOBAL( clk),  VCC,  reset,  VCC);
  _EQ003 =  din2 &  load
         #  dout2 & !load;

-- Node name is 'dout3' = 'p_state3' 
-- Equation name is 'dout3', location is LC023, type is output.
 dout3   = DFFE( _EQ004 $  GND, GLOBAL( clk),  VCC,  reset,  VCC);
  _EQ004 =  din3 &  load
         #  dout3 & !load;

-- Node name is 'dout4' = 'p_state4' 
-- Equation name is 'dout4', location is LC021, type is output.
 dout4   = DFFE( _EQ005 $  GND, GLOBAL( clk),  VCC,  reset,  VCC);
  _EQ005 =  din4 &  load
         #  dout4 & !load;

-- Node name is 'dout5' = 'p_state5' 
-- Equation name is 'dout5', location is LC020, type is output.
 dout5   = DFFE( _EQ006 $  GND, GLOBAL( clk),  VCC,  reset,  VCC);
  _EQ006 =  din5 &  load
         #  dout5 & !load;

-- Node name is 'dout6' = 'p_state6' 
-- Equation name is 'dout6', location is LC019, type is output.
 dout6   = DFFE( _EQ007 $  GND, GLOBAL( clk),  VCC,  reset,  VCC);
  _EQ007 =  din6 &  load
         #  dout6 & !load;

-- Node name is 'dout7' = 'p_state7' 
-- Equation name is 'dout7', location is LC017, type is output.
 dout7   = DFFE( _EQ008 $  GND, GLOBAL( clk),  VCC,  reset,  VCC);
  _EQ008 =  din7 &  load
         #  dout7 & !load;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                          c:\documents and settings\reg.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,285K