library ieee;
use ieee.std_logic_1164.all;
entity reg is
    port(
         clk:in std_logic;
         reset:in std_logic;
         load:in std_logic;
         din:in std_logic_vector(7 downto 0);
         dout:out std_logic_vector(7 downto 0)
    );
end reg;
architecture reg_arch of reg is
signal n_state,p_state: std_logic_vector(7 downto 0);
begin
   dout<=p_state;
    com:process(p_state,load,din)
   begin
      n_state<=p_state;
      if(load='1')then
           n_state<=din;
      end if;
   end process;
   state:process(clk,reset)
   begin
   if(reset='0')then
      p_state<=(others=>'1');
   elsif(clk'event and clk='1')then
      p_state<=n_state;
   end if;
  end process state;
end reg_arch;