library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ch4_6_1 is
port(
     dataout:out std_logic_vector(6 downto 0);
     addr   :in  std_logic_vector(3 downto 0);
     ce     :in std_logic);
end ch4_6_1;
architecture a of ch4_6_1 is
begin
dataout<="0000001"when addr="0000"and ce='0'else
         "1001111"when addr="0001"and ce='0'else
         "0010010"when addr="0010"and ce='0'else
         "0000110"when addr="0011"and ce='0'else
         "1001100"when addr="0100"and ce='0'else
         "0100100"when addr="0101"and ce='0'else
         "0100000"when addr="1001"and ce='0'else
         "0001111"when addr="1010"and ce='0'else
         "0000000"when addr="1011"and ce='0'else
         "0001100"when addr="1100"and ce='0'else
         "1111111";
   end a;