module design_top (  xn_re, xn_im, start, nfft, nfft_we,  //unload,  fwd_inv, fwd_inv_we, scale_sch, scale_sch_we,	rst, clk, xk_re,	xk_im, xn_index, xk_index,  rfd, busy, dv, edone,	done,	ovflo, locked);input [15:0] xn_re, xn_im;  //Input datainput start;                //FFT start signal//input unload;               //FFT unload datainput [4:0] nfft;           //FFT points (can dynamicaly chnage the size of FFTinput nfft_we;              //Write enable for FFT pointsinput fwd_inv;              //IFFT/FFT control 1'b0/1'b1input fwd_inv_we;           //Write enable for IFFT/FFT controlinput [19:0] scale_sch;     //FFT schedule inputinput scale_sch_we;         //Write enable for FFT schedule inputinput rst;                  //DCM resetinput clk;                  //Input clockoutput [15:0] xk_re, xk_im; //Output dataoutput [9:0] xn_index;      //Input data indexoutput [9:0] xk_index;      //Onput data indexoutput rfd;                 //FFT ready for dataoutput busy;                //FFT busyoutput dv;                  //Output data validoutput edone;               //FFT done will transition at end of resultoutput done;                //FFT early done (one clock cycle before done)output ovflo;               //FFT arithmetic overflow indicator (active during unload)output locked;              //DCM lock signalwire clk_ibufgd, clk0_dcm, locked_dcm, clk0_bufgd;reg [15:0] xn_re_int, xn_im_int;reg start_int;//reg unload_int;reg [4:0] nfft_int;reg nfft_we_int;reg fwd_inv_int;reg fwd_inv_we_int;reg [19:0] scale_sch_int;reg scale_sch_we_int;wire [15:0] xk_re_int, xk_im_int;wire [9:0] xn_index_int, xk_index_int;wire rfd_int;wire busy_int;wire dv_int;wire edone_int;wire done_int;wire ovflo_int;reg [15:0] xk_re_reg, xk_im_reg;reg [9:0] xn_index_reg, xk_index_reg;reg rfd_reg;reg busy_reg;reg dv_reg;reg edone_reg;reg done_reg;reg ovflo_reg;/************************************************************************ * instantiation                                                        * ************************************************************************/IBUFG U0 (.O(clk_ibufgd), .I(clk));DCM DCM_inst (  .CLKIN(clk_ibufgd),   // Clock input (from IBUFG, BUFG or DCM)  .CLKFB(clk0_bufgd),   // DCM clock feedback  .RST(rst),            // DCM asynchronous reset input  .CLK0(clk0_dcm),      // 0 degree DCM CLK ouptput  .LOCKED(locked_dcm)   // DCM LOCK status output   );BUFG U2 (.O(clk0_bufgd), .I(clk0_dcm));//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAGmy_radix2_xfft1024 U3 (	.xn_re(xn_re_int),	.xn_im(xn_im_int),	.start(start_int),//	.unload(unload_int),	.nfft(nfft_int),	.nfft_we(nfft_we_int),	.fwd_inv(fwd_inv_int),	.fwd_inv_we(fwd_inv_we_int),	.scale_sch(scale_sch_int),	.scale_sch_we(scale_sch_we_int),	.sclr(!locked),	.clk(clk0_bufgd),	.xk_re(xk_re_int),	.xk_im(xk_im_int),	.xn_index(xn_index_int),	.xk_index(xk_index_int),	.rfd(rfd_int),	.busy(busy_int),	.dv(dv_int),	.edone(edone_int),	.done(done_int),	.ovflo(ovflo_int));// INST_TAG_END ------ End INSTANTIATION Template ---------  always @(posedge clk0_bufgd)  begin    xn_re_int <= xn_re;    xn_im_int <= xn_im;    start_int <= start;//    unload_int <= unload;    nfft_int <= nfft;    nfft_we_int <= nfft_we;    fwd_inv_int <= fwd_inv;    fwd_inv_we_int <= fwd_inv_we;    scale_sch_int <= scale_sch;    scale_sch_we_int <= scale_sch_we;    xk_re_reg <= xk_re_int;    xk_im_reg <= xk_im_int;    xn_index_reg <= xn_index_int;    xk_index_reg <= xk_index_int;    rfd_reg <= rfd_int;    busy_reg <= busy_int;    dv_reg <= dv_int;    edone_reg <= edone_int;    done_reg <= done_int;    ovflo_reg <= ovflo_int;  end  assign xk_re = xk_re_reg;  assign xk_im = xk_im_reg;  assign xn_index = xn_index_reg;  assign xk_index = xk_index_reg;  assign rfd = rfd_reg;  assign busy = busy_reg;  assign dv = dv_reg;  assign edone = edone_reg;  assign done = done_reg;  assign ovflo = ovflo_reg;  assign locked = locked_dcm;endmodule