/*********************************************Input 9.375 MHz (period - 106.67ns) signal.This should apper in bin 192Fs = 50 MHz (period - 20 ns)FFT Points = 1024Bin Size = 50 MHz / 1024 points = 48.828 kHz9.375 MHz / 48.828 kHz = Bin 192*********************************************/`timescale 1ns/1psmodule design_top_tb_tf();  parameter CLOCK_PERIOD = 20;  parameter HALF_CLOCK_PERIOD = CLOCK_PERIOD/2;// Inputs    reg [15:0] xn_re;    reg [15:0] xn_im;    reg start;//    reg unload;    reg [3:0] nfft;    reg nfft_we;    reg fwd_inv;    reg fwd_inv_we;    reg [19:0] scale_sch;    reg scale_sch_we;    reg rst;    reg clk;// Outputs    wire [15:0] xk_re;    wire [15:0] xk_im;    wire [9:0] xn_index;    wire [9:0] xk_index;    wire rfd;    wire busy;    wire dv;    wire edone;    wire done;    wire ovflo;    wire locked;// File io    reg [8*80-1:0] error_string_reg;    integer error_number;    integer infile, i;    reg [15:0] data_in;// Instantiate the UUT    design_top uut (        .xn_re(xn_re),         .xn_im(xn_im),         .start(start), //        .unload(unload),         .nfft(nfft),         .nfft_we(nfft_we),         .fwd_inv(fwd_inv),         .fwd_inv_we(fwd_inv_we),         .scale_sch(scale_sch),         .scale_sch_we(scale_sch_we),         .rst(rst),         .clk(clk),         .xk_re(xk_re),         .xk_im(xk_im),         .xn_index(xn_index),         .xk_index(xk_index),         .rfd(rfd),         .busy(busy),         .dv(dv),         .edone(edone),         .done(done),         .ovflo(ovflo),        .locked(locked)        );// Clock  always  begin    #HALF_CLOCK_PERIOD clk=~clk;  end// Data  initial  begin    clk          = 0;    //initial state of clk    rst          = 1;    //start with DCM in reset    start        = 0;        xn_im        = 0;//    unload       = 0;    nfft         = 10;   //4'b1010  1024pt    nfft_we      = 0;    fwd_inv      = 1;    //FFT=1'b1 IFFT=1'b0    fwd_inv_we   = 0;    scale_sch    = 0;    scale_sch_we = 0;    #(100+(CLOCK_PERIOD))                       //wait for GSR      rst          = 1'b0;                      //relese reset    @(posedge locked);                          //wait for DCM lock    #((HALF_CLOCK_PERIOD)+(CLOCK_PERIOD*2))      nfft_we      = 1'b1;      fwd_inv_we   = 1'b1;      scale_sch    = 20'b01010101010101010101;      scale_sch_we = 1'b1;    #CLOCK_PERIOD      nfft_we      = 1'b0;      fwd_inv_we   = 1'b0;      scale_sch_we = 1'b0;    #CLOCK_PERIOD      start        = 1'b1;                      //start loading and transform    #CLOCK_PERIOD      start        = 1'b0;//    #(CLOCK_PERIOD*2048)//      unload       = 1'b1;//    #CLOCK_PERIOD//      unload       = 1'b0;     end  initial  begin    infile = $fopen("sine_9_375mhz.dat", "r"); //open file    error_string_reg = 0;    error_number = 0;    i =0;    xn_re  = 0;    data_in = 0;        if (infile == 0) begin  //check if file was properly opened and if not, produce error and exit            error_number = $ferror(infile, error_string_reg);      $display("Error: File, input.dat could not be opened due to the following error:\n %d: %s",                error_number, error_string_reg);      $stop;    end    #CLOCK_PERIOD  //push data to negative edge transition    while ($fscanf(infile, "%d\n", data_in) != -1) begin      xn_re = data_in;      i = i +1;      //line index that returns the line number of the input file      #CLOCK_PERIOD;    end    $fclose(infile); //close file    #(CLOCK_PERIOD*10)    $display("Simulation successful (not a failure).  No problems detected.");    $stop;  endendmodule