# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = D:\training\SAP\DSP\Projects\UpdatingExample\FFT\81\81i_radix2_xfft1024_v3_1_verSET speedgrade = -4SET simulationfiles = StructuralSET asysymbol = TrueSET addpads = FalseSET device = xc2v1000SET implementationfiletype = ngcSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = bg575SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex2SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Fast_Fourier_Transform family Xilinx,_Inc. 3.2# END Select# BEGIN ParametersCSET scaling_options=ScaledCSET create_rpm=falseCSET ce=falseCSET run_time_configurable_transform_length=trueCSET output_data_width=16CSET output_ordering=Bit_Reversed_OrderCSET fast_phase_factor=falseCSET memory_options_data=Block_RamCSET number_of_stages_using_block_ram_for_data_and_phase_factors=3CSET ovflo=trueCSET rounding_modes=TruncationCSET component_name=my_radix2_xfft1024CSET memory_options_phase_factors=Block_RamCSET fast_butterfly=falseCSET transform_length=1024CSET implementation_options=Radix_2_Minimum_ResourcesCSET fast_complex_mult=falseCSET sclr=trueCSET optimize_for_speed_using_xtreme_dsp_slices=falseCSET input_width=16CSET phase_factor_width=16# END ParametersGENERATE