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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
my_radix2_xfft1024 YourInstanceName (
	.xn_re(xn_re),
	.xn_im(xn_im),
	.start(start),
	.nfft(nfft),
	.nfft_we(nfft_we),
	.fwd_inv(fwd_inv),
	.fwd_inv_we(fwd_inv_we),
	.scale_sch(scale_sch),
	.scale_sch_we(scale_sch_we),
	.sclr(sclr),
	.clk(clk),
	.xk_re(xk_re),
	.xk_im(xk_im),
	.xn_index(xn_index),
	.xk_index(xk_index),
	.rfd(rfd),
	.busy(busy),
	.dv(dv),
	.edone(edone),
	.done(done),
	.ovflo(ovflo));

// INST_TAG_END ------ End INSTANTIATION Template ---------