/*******************************************************/
/*This is the Linker Command File for the TMS320C55509a*/
/*******************************************************/
-l rts55x.lib
/*-l 55ximagex.lib*/
-heap 0x700
-stack 0xa00
-sysstack 0x400


MEMORY
{
	PAGE 0:

		MMR     : origin = 0000000h, length = 00000c0h 
		SPRAM   : origin = 00000c0h, length = 0000040h
		VECS    : origin = 0000100h, length = 0000100h
		DRAM0  : origin = 0000200h, length = 0003E00h
		DRAM1  : origin = 0004000h, length = 0004000h
		DRAM2  : origin = 0008000h, length = 0004000h
		DRAM3  : origin = 000c000h, length = 0004000h

		SRAM0  : origin = 0010000h, length = 0004000h
		SRAM1  : origin = 0014000h, length = 0008000h
		/*SRAM2  : origin = 0018000h, length = 0004000h*/
		SRAM3  : origin = 001c000h, length = 0004000h
		SRAM4  : origin = 0020000h, length = 0020000h
		/*SRAM5  : origin = 0030000h, length = 0010000h*/
		SRAM6  : origin = 0040000h, length = 0010000h
		/*
		SRAM7  : origin = 002c000h, length = 0004000h
		SRAM8  : origin = 0030000h, length = 0004000h
		SRAM9  : origin = 0034000h, length = 0004000h
		SRAM10 : origin = 0038000h, length = 0004000h
		SRAM11 : origin = 003c000h, length = 0004000h
		SRAM12 : origin = 0040000h, length = 0004000h
		SRAM13 : origin = 0044000h, length = 0004000h
		SRAM14 : origin = 0048000h, length = 0004000h
		SRAM15 : origin = 004c000h, length = 0004000h*/

		CE0     : origin = 0050000h, length = 03b0000h 
		CE1     : origin = 0400000h, length = 0400000h
		CE2     : origin = 0800000h, length = 0400000h
		CE3     : origin = 0c00000h, length = 03f8000h

		PDROM   : origin = 0ff8000h, length = 07f00h
		VECS    : origin = 0ffff00h, length = 00100h   /* reset vector */
}       

 
SECTIONS
{
		.vectors  : {} > VECS  PAGE 0       /* interrupt vector table */
        .cinit   : {} > SRAM0 PAGE 0
        .text    : {} > SRAM1 PAGE 0
     /*   isrs     : {} > SRAM2 PAGE 0*/

        .stack   : {} > DRAM0 PAGE 0
        .sysstack: {} > DRAM0 PAGE 0
        .sysmem  : {} > DRAM1 PAGE 0
        .data    : {} > DRAM1 PAGE 0
        .bss     : {} > DRAM1 PAGE 0
        .const   : {} > SRAM0 PAGE 0

        .cio     : {} > DRAM1 PAGE 0
        .csldata:  {} > DRAM0 PAGE 0
		.notice  : {} > SRAM0 PAGE 0
		
		.onebuf  : {} > SRAM3 PAGE 0
		.bitstream  : {} > SRAM0 PAGE 0
		.tmpbuf : {} >DRAM2 PAGE 0
		dctcoef : {} >DRAM2 PAGE 0

		.pic1   : {} > SRAM4 PAGE 0
		.pic2   : {} > SRAM4 PAGE 0
		.pic3   : {} > SRAM4 PAGE 0
}