//###########################################################################
//
// FILE:	DSP281x_Ini.c
//
// TITLE:	DSP281x CPU Initialization & Support Functions.
//
// NOTES:   All DSP281x CPU initialization is list in the file.
//          CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
//          other realtime operating systems.  
//
//          Do not use these two timers in your application if you ever plan
//          on integrating DSP-BIOS or another realtime OS. 
//
//          For this reason, the code to manipulate these two timers is
//          commented out and not used in these examples.
//           
//###########################################################################
//
//  Ver | dd mmm yyyy |  Who  | Description of changes
// =====|=============|=======|==============================================
//  1.00| 17 Mar 2004 | Y.Z.Y | First Version V1.0
//###########################################################################
//
//  Ver | dd  mmm  yyyy |  Who  | Description of changes
// =====|=============|=======|===============================================
//  1.00| 30  June 2004 | Y.Z.Y | Second Version V2.0
//###########################################################################

#include  "F2812reg.h"
#include  "Main.h"
#include  "DSP281x_ECan.h"

// volatile C28X_TIMER * Timer0 = (C28X_TIMER *)0xc00;

//===========================================================================
// InitSysCtrl:
// This function initializes the System Control registers to a known state.
// - Disables the watchdog
// - Set the PLLCR for proper SYSCLKOUT frequency 
// - Set the pre-scaler for the high and low frequency peripheral clocks
// - Enable the clocks to the peripherals
//===========================================================================

void InitSysCtrl(void)
{
    EALLOW;             /* Enable accesses to protected registers */
    PLLCR  = PLLSCALE;
/* Enable  ADC,EVA,EVB High Speed Mode; SCIA, SCIB, SPI, MCBSP Low Speed Mode;
   Ecan (System clock) */
    PCLKCR = 0x4d0b; 
    HISPCP = 0x0000;    /* CLKIN/1 */
    LOSPCP = 0x0002;    /* CLKIN/4 */
    EDIS;               /* Disable accesses to protected registers */
}

//===========================================================================
// KickDog:
// This function resets the watchdog timer.
// Enable this function for using KickDog in the application 
//===========================================================================

void KickDog(void)
{
    EALLOW;
    WDKEY = 0x0055;
    WDKEY = 0x00AA;
    EDIS;
}

//===========================================================================
// DisableDog:
// This function disables the watchdog timer.
//===========================================================================

void DisableDog(void)
{
    EALLOW;
    WDCR = 0x0068;
    EDIS;
}

//===========================================================================
// ConfigCPUTimers: 
// This function initializes CPU timer0 to a known state.
//===========================================================================

void ConfigCpuTimers( void )
{
    /* Setting Timer 1ms*/
    EALLOW;
    Timer0.Timer = T0PERIOD; 
    Timer0.Period = T0PERIOD;
    Timer0.Prescale = 0;
    Timer0.Control = 0x4830; /* enable interrupt;Free run;reload */
    EDIS;
}

void TimersStart( void)
{
    Timer0.Control &= 0xffef; 
}

void TimersStop( void)
{
    Timer0.Control |= 0x0010; 
}

//===========================================================================
// GpioInit:
// This function initializes the Gpio to a known state.
//===========================================================================

void GpioInit( void )
{
    EALLOW;
    GPAMUX = 0x0300;  /* Enable Cap1, Cap2 */
    GPBMUX = 0x0300;  /* Enable Cap4, Cap5 */
    GPEMUX = 0x0003;  /* Enable XINT1, XINT2 */
    GPFMUX = 0x00FF;  /* Enable SCIA, Ecan, SPI */ 
    GPGMUX = 0x0030;  /* Enable SCIB */
    
    GPADIR = 0x0000;  /*configure the gpio a as input*/
    GPBDIR = 0x0000;
    GPEDIR = 0x0000;
    GPFDIR = 0x4050;  /* SCIA TX RX; Ecan Tx Rx; Config the XF as GPIO(output) 2004/9/14*/ 
    GPGDIR = 0x0010;  /* SCIB TX RX*/
    EDIS;
}

//===========================================================================
// EvInit:
// This function initializes the EV to a known state.
//===========================================================================

void EvInit( void )
{
    //Initialize the EVA 
    GPTCONA  = 0x0400;     // Use the timer2 to start the ADC ( underflow )
    T1CNT    = 0x0000;
    T1CON    = 0x1040;     // EVT1CLK = HSPCLK/1, T1CON.6(TENABLE) = 1(Enable time1)
    T1PR     = EVT1PERIOD;
    T2CNT    = 0x0000;
    T2CON    = 0x1300;     // EVT2CLK = HSPCLK/8, T2CON.6(TENABLE) = 0(disnable time2)
    T2PR     = EVT2PERIOD; // Default value
    // Cap 1,2,3
    CAPFIFOA = 0x0000;     // Each two generates interrupt
    CAPCONA  = 0x0000;     // Reset cap1,2,3
    NOP;
    CAPCONA  = 0xB6FF;     // Using GP Timer 1 and both edge detection for cap1,2,3
    // Interrupts mask
    EVAIMRA  = 0x0000;     // Disnable T1PINT
    //EVAIMRB = 0x0001;      // Enable T2PINT
    EVAIMRC  = 0x0003;     // Enable cap1 and cap2 interrupts
    
    //Initialize the EVB 
    GPTCONB  = 0x0000;
    T3CNT    = 0x0000;
    T3CON    = 0x1040;     // EVT3CLK = HSPCLK/1, T3CON.6(TENABLE) = 1(Enable time3)
    T3PR     = EVT3PERIOD;
    
    T4CNT    = 0x0000;
    T4CON    = 0x1700;     // EVT4CLK = HSPCLK/128, T4CON.6(TENABLE) = 0(Disnable time4)    
    T4PR     = EVT4PERIOD;
    //Cap 4,5,6
    CAPFIFOB = 0x0000;     // Each two generates interrupt
    CAPCONB  = 0x0000;     // Reset cap3,4,5
    NOP;
    CAPCONB  = 0xB6FF;     // Using GP Timer 3 and both edge detection for cap4,5,6
    // Interrupts mask
    EVBIMRA  = 0x0000;     // Disable T3PINT 
    EVBIMRB = 0x0001;      // Enable T4PINT
    EVBIMRC  = 0x0003;     // Enable cap4 and cap5 interrupts
}

//===========================================================================
// SciInit:
// This function initializes the SCIs to a known state.
//===========================================================================

void SciInit( void )
{
    //setup SCIA
    SCIFFTXA  = 0x0000; // reset transmit chanel
    SCIFFRXA  = 0x0000; // reset transmit chanel
    SCICCRA   = 0x07;   // one stop bit;no parity;8 bit Data
    SCICTL1A  = 0x03;
    SCIHBAUDA = SCIABAUDH;
    SCILBAUDA = SCIABAUDL;
    SCICTL2A  = 0x03;   // Enable RI,TI
    SCICTL1A  = 0x23;   // enable Recieve and Transmit
    SCIFFTXA  = 0xC020; // Enable interrupt, Triger level set to min
    SCIFFRXA  = 0x601F; // disable interrupt, Triger Level set to max
    SCIFFCTA  = 0x0008;
    SCIPRIA   = 0x0000;
    //setup SCIB
    SCIFFTXB  = 0x0000; // reset transmit chanel
    SCIFFRXB  = 0x0000; // reset transmit chanel
    SCICCRB   = 0x07;   // one stop bit;no parity;8 bit Data
    
    SCICTL1B  = 0x03;
    SCIHBAUDB = SCIBBAUDH;
    SCILBAUDB = SCIBBAUDL;
    SCICTL2B  = 0x03;   // Enable RI,TI
    SCICTL1B  = 0x23;   // enable Recieve and Transmit
    
    SCIFFTXB  = 0xC020; // Enable TX Interrupt
    SCIFFRXB  = 0x3069; // enable RX Interrupt, Triger Level set to 9 
    SCIFFCTB  = 0x0008;
    SCIPRIB   = 0x0000;
}

//===========================================================================
// AdcInit:
// This function initializes the ADC to a known state.
//===========================================================================

void AdcInit()
{
//	extern void DSP28x_usDelay(uint32 Count);
	
    // To powerup the ADC the ADCENCLK bit should be set first to enable
    // clocks, followed by powering up the bandgap and reference circuitry.
    // After a 5ms delay the rest of the ADC can be powered up. After ADC
    // powerup, another 20us delay is required before performing the first
    // ADC conversion. Please note that for the delay function below to
    // operate correctly the CPU_CLOCK_SPEED define statement in the
    // DSP28_Examples.h file must contain the correct CPU clock period in
    // nanoseconds. For example:
	
    ADCTRL3 = 0x00C0;       // Power up bandgap/reference circuitry
    DELAY_US(ADC_usDELAY);  // Delay before powering up rest of ADC
    ADCTRL3 |= 0x0020;      // Power up rest of ADC
    DELAY_US(ADC_usDELAY2); // Delay after powering up ADC
    
    // Emulation suspend immediately stop
    // FCLKv = CLK/1
    // Continuous conversation mode
    // Cascaded sequencer operation
    ADCTRL1 = 0x3F10;       // Width of SOC pulse is 16 ADCCLK period, Start-stop mode
    ADCTRL3 |= 0x000C;      // HSPCLK/[12*(ADCTRL1[7] + 1)] = 12.5MHz
                            // Sequential sampling mode
    ADCTRL2 = 0x4900;       // Enable sequencer 1 interrupts, EVA start SEQ is allowed
    ADCMAXCONV = 0x0003;    // 4 channel AD sequence
    ADCCHSELSEQ1 = 0x3210;
//    ADCCHSELSEQ2 = 0x7654;
//    ADCCHSELSEQ3 = 0xBA98;
//    ADCCHSELSEQ4 = 0x0EDC; //SEQA0 - SEQA7,SEQB0 - SEQB6
    
}
//===========================================================================
// XintfInit:
// This function initializes the Xintf to a known state.
//===========================================================================

void XintfInit( void )
{
    XTIMING2 = 0x031229;
    XINTCNF2 = 0x10008;
    XBANK    = 0x0002;
}

//===========================================================================
// XintInit:
// This function initializes the XINT1,2 to a known state.
//===========================================================================

void XintInit( void )
{
    EALLOW;
    XINT1CR = 0x0007;
    XINT2CR = 0x0007;
    EDIS;
}

//===========================================================================
// ECanInit: 
// This function initializes the eCAN module to a known state.
//===========================================================================

void ECanInit( void )
{
    // Only 32.bit accesses are allowed to the control and status registers. 
    // This restriction does not apply to the mailbox RAM area.
    EALLOW;
    CANTIOC = 0x00000008; // Configure eCAN RX and TX pins
    CANRIOC = 0x00000008; // for eCAN transmissions using eCAN regs
    CANMC = 0x00000000;
    // Initialize all bits of 'Master Control Field' to zero
    // Some bits of MSGCTRL register come up in an unknown state. For proper operation,
    // all bits (including reserved bits) of MSGCTRL must be initialized to zero
    ECanaMboxes.MBOX0.MSGCTRL  = 0x00000000;  
    ECanaMboxes.MBOX1.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX2.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX3.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX4.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX5.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX6.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX7.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX8.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX9.MSGCTRL  = 0x00000000; 
    ECanaMboxes.MBOX10.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL = 0x00000000;
	// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution. 
    // Clear all TAn bits
	CANTA = 0xFFFFFFFF;
    // Clear all RMPn bits
	CANRMP = 0xFFFFFFFF;
    // Clear all interrupt flag bits
    CANGIF0 = 0xFFFFFFFF;
	CANGIF1 = 0xFFFFFFFF;
	// Configure bit timing parameters
    CANMC |= 0x00001000; // Set CCR(CANMC:12) = 1
	while ( (CANES&0x00000010) == 0) {} // Wait for CCE bit to be set..
	CANBTC = BITTIMING;
	CANMC &= 0xFFFFEFFF; // Set CCR(CANMC:12) = 0
	while ( (CANES&0x00000010) != 0) {} // Wait for CCE bit to be cleared..
	// Disable all Mailboxes
	CANME = 0x00000000;
    EDIS;
}
//===========================================================================
// No more.
//===========================================================================