Analysis & Synthesis report for seg71
Wed Dec 20 20:14:54 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Parameter Settings for Inferred Entity Instance: lpm_counter:cnt_scan_rtl_0
  8. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Dec 20 20:14:54 2006    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; seg71                                    ;
; Top-level Entity Name       ; seg71                                    ;
; Family                      ; MAX7000S                                 ;
; Total macrocells            ; 32                                       ;
; Total pins                  ; 18                                       ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option                                                               ; Setting         ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device                                                               ; EPM7128SLC84-15 ;               ;
; Top-level entity name                                                ; seg71           ; seg71         ;
; Family name                                                          ; MAX7000S        ; Stratix       ;
; Use smart compilation                                                ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                                  ; Off             ; Off           ;
; Preserve fewer node names                                            ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                            ; Off             ; Off           ;
; Verilog Version                                                      ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                         ; VHDL93          ; VHDL93        ;
; State Machine Processing                                             ; Auto            ; Auto          ;
; Extract Verilog State Machines                                       ; On              ; On            ;
; Extract VHDL State Machines                                          ; On              ; On            ;
; Add Pass-Through Logic to Inferred RAMs                              ; On              ; On            ;
; NOT Gate Push-Back                                                   ; On              ; On            ;
; Power-Up Don't Care                                                  ; On              ; On            ;
; Remove Redundant Logic Cells                                         ; Off             ; Off           ;
; Remove Duplicate Registers                                           ; On              ; On            ;
; Ignore CARRY Buffers                                                 ; Off             ; Off           ;
; Ignore CASCADE Buffers                                               ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                                ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                            ; Off             ; Off           ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A           ; Auto            ; Auto          ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A            ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                                       ; Off             ; Off           ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A         ; Speed           ; Speed         ;
; Allow XOR Gate Usage                                                 ; On              ; On            ;
; Auto Logic Cell Insertion                                            ; On              ; On            ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4               ; 4             ;
; Auto Parallel Expanders                                              ; On              ; On            ;
; Auto Open-Drain Pins                                                 ; On              ; On            ;
; Remove Duplicate Logic                                               ; On              ; On            ;
; Auto Resource Sharing                                                ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A   ; 100             ; 100           ;
; Ignore translate_off and translate_on Synthesis Directives           ; Off             ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                   ; On              ; On            ;
; HDL message level                                                    ; Level2          ; Level2        ;
+----------------------------------------------------------------------+-----------------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                           ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                                                       ;
+----------------------------------+-----------------+------------------------+------------------------------------------------------------------------------------+
; seg71.v                          ; yes             ; User Verilog HDL File  ; I:/Mars-7128-S Altera CPLD開發(fā)板/示例程序/Verilog/接口實(shí)驗(yàn)/7段數(shù)碼管/seg71/seg71.v ;