-- VHDL Test Bench Created from source file sc_corproc.vhd -- 12/07/06  11:47:39---- Notes: -- 1) This testbench template has been automatically generated using types-- std_logic and std_logic_vector for the ports of the unit under test.-- Lattice recommends that these types always be used for the top-level-- I/O of a design in order to guarantee that the testbench will bind-- correctly to the timing (post-route) simulation model.-- 2) To use this template as your testbench, change the filename to any-- name of your choice with the extension .vhd, and use the "source->import"-- menu in the ispLEVER Project Navigator to import the testbench.-- Then edit the user defined section below, adding code to generate the -- stimulus for your design.-- 3) VHDL simulations will produce errors if there are Lattice FPGA library -- elements in your design that require the instantiation of GSR, PUR, and-- TSALL and they are not present in the testbench. For more information see-- the How To section of online help.  --LIBRARY ieee;LIBRARY generics;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_signed.ALL;USE ieee.std_logic_arith.ALL;USE generics.components.ALL;ENTITY cordic_tst ISEND cordic_tst;ARCHITECTURE behavior OF cordic_tst IS 	COMPONENT sc_corproc	PORT(		clk : IN std_logic;		ena : IN std_logic;		Ain : IN signed(15 downto 0);          		sin : OUT signed(15 downto 0);		cos : OUT signed(15 downto 0)		);	END COMPONENT;	SIGNAL clk :  std_logic:='0';	SIGNAL ena :  std_logic:='0';	SIGNAL Ain :  signed(15 downto 0):=(others=>'0');	SIGNAL sin :  signed(15 downto 0);	SIGNAL cos :  signed(15 downto 0);	   constant clk_period : time :=20 ns;   BEGIN		clk<= (not clk) after (clk_period/2);	uut: sc_corproc PORT MAP(		clk => clk,		ena => ena,		Ain => Ain,		sin => sin,		cos => cos	);-- *** Test Bench - User Defined Section ***	   tb : PROCESS   BEGIN    	wait for (clk_period*5);    	ena<='0';    	Ain<=(others=>'0');		wait for (clk_period*4);		Ain<=X"0000";		ena<='1';		wait for (clk_period*40);		ena<='0';		wait for (clk_period*1);		ena<='1';		Ain<=X"1555";		wait for (clk_period*40);		ena<='0';		wait for (clk_period*1);		ena<='1';		Ain<=X"2000";		wait for (clk_period*40);		ena<='0';		wait for (clk_period*1);		ena<='1';		Ain<=X"2AAA";		wait for (clk_period*40);		ena<='0';		wait for (clk_period*1);		ena<='1';		Ain<=X"4000";		wait for (clk_period*40);		ena<='0';		wait for 20 ns;		      wait; -- will wait forever   END PROCESS;-- *** End Test Bench - User Defined Section ***END;