/*mcbsp.h*/
/*串口0定義*/
#ifndef mcbsp5409_h
#define mcbsp5409_h
extern volatile unsigned MCBSP0_DRR20;	/* Data receive register2 of McBSP0 */
asm("_MCBSP0_DRR20 .set 0x20");

extern volatile unsigned MCBSP0_DRR10;	/* Data receive register1 McBSP0 */
asm("_MCBSP0_DRR10 .set 0x21");

extern volatile unsigned MCBSP0_DXR20;	/* Data transimit register2 McBSP0 */
asm("_MCBSP0_DXR20 .set 0x22");

extern volatile unsigned MCBSP0_DXR10;	/* Data transimit register1 McBSP0 */
asm("_MCBSP0_DXR10 .set 0x23");

extern volatile unsigned MCBSP0_SPSA0; /* McBSP0 subbank address register */
asm("_MCBSP0_SPSA0 .set 0x38");

extern volatile unsigned MCBSP0_SPSD0;	/* McBSP0 subbank data register */
asm("_MCBSP0_SPSD0 .set 0x39");


#define 	SPCR1_SUBADDR	0x00	/* Serial port control register 1 */
#define		SPCR2_SUBADDR	0x01	/* Serial port control register 2 */
#define		RCR1_SUBADDR	0x02	/* Receive control register 1 */
#define		RCR2_SUBADDR	0x03	/* Receive control register 2 */
#define		XCR1_SUBADDR	0x04	/* Transmit control register 1 */
#define		XCR2_SUBADDR	0x05	/* Transmit control register 2 */
#define		SRGR1_SUBADDR	0x06	/* Sample rate generator register 1 */
#define		SRGR2_SUBADDR	0x07	/* Sample rate generator register 2 */
#define		MCR1_SUBADDR	0x08	/* Multichannel  register 1 */
#define		MCR2_SUBADDR	0x09	/* Multichannel register 2 */
#define		PCERA0_SUBADDR	0x0a	/* Receive channel enable register partition A */
#define		PCERB0_SUBADDR	0x0b	/* Receive channel enable register partition B */
#define		XCERA0_SUBADDR	0x0c	/* Transmit channel enable register partition A */
#define		XCERB0_SUBADDR	0x0d	/* Transmit channel enable register partition B */
#define		PCR_SUBADDR	0x0e	/* Pin control register */
/*SPCR1*/
#define CLKSTP_s	0x1800 /*clock starts w/o delay SPI 選擇*/   
#define RINTM_s		0x0000 /*int by new frame sync*/
#define RRST_s	   	0x0001 /*receiver enable*/  
#define DLB_s		0x0000 /*digital loop back mode enabled , 數字反饋模式*/    
#define RJUST_s		0x0000 /*right-justify and zero-fill msbs in drr[1,2]*/
#define DXENA_s		0x0000 /* dx enabler is on