;
;   Start of Zoran Standard Header
;   Copyright (c) 2003 - 2004 Zoran Corporation.
;   
;   
;   All rights reserved.  Proprietary and confidential.
;   
;   DESCRIPTION for boot.s
;   	Boot code for the Firestarter Reference Boards
;   
;   End of Zoran Standard Header
;
;/******************************************************************************
;*
;* Author:              Mark Dobrosielski
;*
;* Description:         Source file for the Firestarter boot code.
;*
;* Revision History:
;* Date        Author   Description
;* ----        ------   -----------
;* 10/24/02    Dobro    Included defs.s instead of int_defs.s
;*                      System Bus set up for faster Flash access, access to
;*                      both Flash chips, and access to CS2 & CS3 (for FAX and
;*                      the new & improved UI).
;*                      Updated comments.
;* 10/25/02    Dobro    Modified code move routines, since vector table is no
;*                      longer contiguous with the code.  There is a gap to
;*                      leave space for memory the debugger uses.
;*                      Combined files boot.s and bootram.s (used instead of
;*                      boot.s for RAM targets).  The predefine TARGET_RAM,
;*                      if defined, selects the RAM version.  Otherwise, the
;*                      ROM/FLASH version is built.
;*
;* 02/17/04		Gary L
;*				John C	Adapted Dobro's and TPS boot code for use with the
;*						multiple Firestarter systems.
;******************************************************************************/
	IMPORT InstrCacheEnable
	IMPORT DataCacheEnable
	IMPORT InvalidateInstrCache
	IMPORT InvalidateDataCache
    IMPORT SetOvlRegs

;/*************************************************************************/
;/*               boot.s for ROM/FLASH targets                            */
;/*************************************************************************/
	INCLUDE fireregs.inc
	INCLUDE overlay.inc
	INCLUDE defs.inc

;/*************************************************************************/
;/*   EXTERNAL VARIABLE/FUNCTION DECLARATIONS                             */
;/*************************************************************************/

;-------------------------------------------------------------
;   Define extern function references. 
;-------------------------------------------------------------
   IF :DEF: TARGET_JUSTBOOT
   ELSE
	IMPORT  INT_Initialize
	IMPORT  INT_IRQ
	ENDIF

; The address of the 1Kb Tightly Coupled Memory (TCM) base

TCMBASE     EQU 0x18000000

;/*************************************************************************/
;/*++++++++++++  BOOT ENTRY POINT ++++++++++++++++++++++++++++++++++++++++*/
;/*    LOCATE AT 0xffff0000 in the scatter load file                      */
;/*************************************************************************/
    AREA VECTORS, CODE, READONLY

VectorTable
    LDR	pc,Reset_Addr
    LDR	pc,Undef_Instr_Addr
    LDR	pc,SWI_Addr
    LDR	pc,Prefetch_Abort_Addr
    LDR	pc,Data_Abort_Addr
    LDR	pc,Reserved_Addr
    LDR	pc,IRQ_Handler_Addr
    LDR	pc,FIQ_Handler_Addr

Reset_Addr              DCD Bootload
Undef_Instr_Addr        DCD UndefInt
SWI_Addr                DCD UndefInt
Prefetch_Abort_Addr     DCD UndefInt
Data_Abort_Addr         DCD UndefInt
Reserved_Addr           DCD UndefInt
FIQ_Handler_Addr        DCD UndefInt

   IF :DEF: TARGET_JUSTBOOT
IRQ_Handler_Addr        DCD UndefInt
   ELSE
	IMPORT	ISR_Interrupt
IRQ_Handler_Addr        DCD ISR_Interrupt
	ENDIF

BootBuildDate
	IMPORT builddate
	IMPORT sys_version
	DCD sys_version
	DCD builddate
	DCD VALID_BUILD_DATE

Load_V_Start
	IMPORT  |Load$$ER_V$$Base|
	DCD     |Load$$ER_V$$Base|

Load_RO_Start
	IMPORT  |Load$$ER_RO$$Base|
	DCD     |Load$$ER_RO$$Base|

Load_RW_Start
	IMPORT  |Load$$ER_RW$$Base|
	DCD     |Load$$ER_RW$$Base|

Exec_V_Start
	IMPORT  |Image$$ER_V$$Base|
	DCD     |Image$$ER_V$$Base|

Exec_V_End
	IMPORT  |Image$$ER_V$$Limit|
	DCD     |Image$$ER_V$$Limit|

Exec_RO_Start
	IMPORT  |Image$$ER_RO$$Base|
	DCD     |Image$$ER_RO$$Base|

Exec_RO_End
	IMPORT  |Image$$ER_RO$$Limit|
	DCD     |Image$$ER_RO$$Limit|

Exec_RW_Start
	IMPORT  |Image$$ER_RW$$Base|
	DCD     |Image$$ER_RW$$Base|

Exec_RW_End
	IMPORT  |Image$$ER_RW$$Limit|
	DCD     |Image$$ER_RW$$Limit|

Exec_ZI_Start
	IMPORT  |Image$$ER_ZI$$ZI$$Base|
	DCD     |Image$$ER_ZI$$ZI$$Base|

Exec_ZI_End
	IMPORT  |Image$$ER_ZI$$ZI$$Limit|
	DCD     |Image$$ER_ZI$$ZI$$Limit|

; The PLLCTR values based based upon the PLL Modulation values
; This table defines the PLLCTR values that correspond to the 
; user selectable value stored in serial flash.
; 
; Note that as the modulation increases, the system clock frequency is
; decreased so that memory will not be overclocked

    IF :DEF: PLL_MODULATION

; Default PLL Modulation value index

DEFAULT_PPLMODVAL EQU     0

PLLCTRval
    DCD      0x00010f29 ; 0     2.5% 129.62 MHz
    DCD      0x00011f06 ; 1     5.0% 126.29 MHz
    DCD      0x00012ee4 ; 2     7.5% 122.95 MHz
    DCD      0x00013ec0 ; 3    10.0% 119.95 MHz
    DCD      0x00014f42 ; 4    None  132.00 MHz
    DCD      0x00014f42 ; 5    None  132.00 MHz
    DCD      0x00014f42 ; 6    None  132.00 MHz
    DCD      0x00014f42 ; 7    None  132.00 MHz

    ENDIF

;/*************************************************************************/
;/*                                                                       */
;/* FUNCTION                                                              */
;/*                                                                       */
;/*      INT_Initialize                                                   */
;/*                                                                       */
;/* DESCRIPTION                                                           */
;/*                                                                       */
;/*      This function sets up the global system stack variable and       */
;/*      transfers control to the target independent initialization       */
;/*      function INC_Initialize.  Responsibilities of this function      */
;/*      include the following:                                           */
;/*                                                                       */
;/*             - Setup necessary processor/system control registers      */
;/*             - Initialize the vector table                             */
;/*             - Setup the system stack pointers                         */
;/*             - Setup the timer interrupt                               */
;/*             - Calculate the timer HISR stack and priority             */
;/*             - Calculate the first available memory address            */
;/*             - Transfer control to INC_Initialize to initialize all of */
;/*               the system components.                                  */
;/*                                                                       */
;/*************************************************************************/
    AREA BOOTSECT, CODE, READONLY
    EXPORT Bootload
	
	ENTRY
Bootload
	LDR   r0, =0x00            ; clear all regs except r13 (sp) 
	LDR   r1, =0x00          
	LDR   r2, =0x00          
	LDR   r3, =0x00  
	LDR   r4, =0x00  
	LDR   r5, =0x00  
	LDR   r6, =0x00  
	LDR   r7, =0x00  
	LDR   r8, =0x00  
	LDR   r9, =0x00  
	LDR   r10, =0x00  
	LDR   r11, =0x00  
	LDR   r12, =0x00  
	LDR   r14, =0x00

	MRS a1, CPSR             ; Pickup current CPSR
	BIC a1, a1,#MODE_MASK    ; Clear the mode bits
	ORR a1, a1,#SUP_MODE     ; Set the supervisor mode bits
	ORR a1, a1,#LOCKOUT      ; disable IRQ/FIQ interrupts
	MSR CPSR_cxsf, a1        ; Setup the new CPSR

;	Reset and recover waiting..
;	According to the design guide, there is some
;	requirement to wait while things reset and recover
;	Not real sure just when this is supposed to happen,
;	but for the time being, lets wait before doing
;	anything.  
;
;	The guide (see Chapter 26) claims a need to wait for
;	1.4mS twice.   The chip is booting with the 48MHz clock
;	and the wait is before the PLL is configured, so the
;	clockrate is 20.8nSec.
;
;	1.4mSec is about 2^16 cycles.   Don't know exactly
;	how many cycles per instruction, (without looking it up)
;	so error on the high side...

	LDR   r0, =0x10000
pause_reset
	SUBS  r0, r0, #1
	BNE   pause_reset
	
	LDR   r0, =0x10000
pause_recover
	SUBS  r0, r0, #1
	BNE   pause_recover
	
   ;; Setup SPI Interface Prescaler Value
SetupSPI
	LDR   r0,=SPICFG1
	LDR   r1,[r0]
	ORR   r1,r1,#0x7
	STR   r1,[r0]


;-------------------------------------------------------------
;                   PLL and DPLL setup
;-------------------------------------------------------------
PLLsetup

   IF :DEF: PLL_MODULATION
   
   ; Clock Modulation is enabled.
   ; The amount of modulation is stored in a variable in the serial flash
   ; The value is a number from 0 - 7. Numbers greater than 3 will disable
   ; PLL Modulation by setting bit 14 of the PLL/Clock Control Register

   IF {FALSE}
   LDR      r0, =PLLMODVAL_PTR
   LDR      r0, [r0,#0]
   MOV      r0, r0, LSR #24
   AND      r0, r0,#7
   ELSE
   LDR      r0, =DEFAULT_PPLMODVAL
   ENDIF

   LDR      r1, =PLLCTRval
   LDR      r0, [r1,r0,LSL #2]
   LDR      r1, =PLLCTR
   STR      r0, [r1]

   ELSE


; 	According to the design guide...
;	Load the PLL Control Register with enable

	LDR   r0, =PLLCTR
	LDR   r1, =PLLCFG 
	STR   r1, [r0]

	ENDIF
   
	IF    (:DEF: ZR4100)
	
; Check for PLL Lock
PllLock
	LDR   r0, =PLLCTR
	LDR   r1, [r0]
	TST   r1, #0x00020000 
	BEQ   PllLock

; Pause for 1.4mSec to let the PLL stabilize
	LDR   r0, =0x10000
pause_loop2
	SUBS  r0, r0, #1
	BNE   pause_loop2
	ENDIF 

   
   IF    (:DEF: ZR4200)
; 	Then Load the DPLL (SDRAM PLL) Control Register with enable

	LDR   r0, =DPLLCTR
	LDR   r1, =0x00014f18 ; from 4200 bsp was 0x00010f18 (mod enabled) 
	STR   r1, [r0]
	
; Check for DPLL Lock
DPllLock
	LDR   r0, =DPLLCTR
	LDR   r1, [r0]
	TST   r1, #0x00020000 
	BEQ   DPllLock

; Pause for 1.4mSec to let the DPLL stabilize
	LDR   r0, =0x10000
pause_loop2
	SUBS  r0, r0, #1
	BNE   pause_loop2

; 	Then Load the VPLL (VOPU PLL) Control Register with enable

	LDR   r0, =0xE0100050  ;VPLLCTR1 (0xE0100000 | 0x00000050)
	LDR   r1, =0x02F3106B   ;0x0001440F 
	STR   r1, [r0]
	
; Check for VPLL Lock
VPllLock
	LDR   r0, =0xE0100050  ;VPLLCTR1 (0xE0100000 | 0x00000050)
	LDR   r1, [r0]
	TST   r1, #0x00020000 
	BEQ   VPllLock
   ENDIF