lis	r1,CFG_INIT_RAM_ADDR@h	ori	r1,r1,CFG_INIT_SP_OFFSET@l	li	r0,0	stwu	r0,-4(r1)	stwu	r0,-4(r1)		/* Terminate call chain */	stwu	r1,-8(r1)		/* Save back chain and move SP */	lis	r0,RESET_VECTOR@h	/* Address of reset vector */	ori	r0,r0, RESET_VECTOR@l	stwu	r1,-8(r1)		/* Save back chain and move SP */	stw	r0,+12(r1)		/* Save return addr (underflow vect) */	GET_GOT	bl	board_init_f#endif /* CONFIG_440 *//*****************************************************************************/#ifdef CONFIG_IOP480	/*----------------------------------------------------------------------- */	/* Set up some machine state registers. */	/*----------------------------------------------------------------------- */	addi	r0,r0,0x0000		/* initialize r0 to zero */	mtspr	esr,r0			/* clear Exception Syndrome Reg */	mttcr	r0			/* timer control register */	mtexier r0			/* disable all interrupts */	addi	r4,r0,0x1000		/* set ME bit (Machine Exceptions) */	oris	r4,r4,0x2		/* set CE bit (Critical Exceptions) */	mtmsr	r4			/* change MSR */	addis	r4,r0,0xFFFF		/* set r4 to 0xFFFFFFFF (status in the */	ori	r4,r4,0xFFFF		/* dbsr is cleared by setting bits to 1) */	mtdbsr	r4			/* clear/reset the dbsr */	mtexisr r4			/* clear all pending interrupts */	addis	r4,r0,0x8000	mtexier r4			/* enable critical exceptions */	addis	r4,r0,0x0000		/* assume 403GCX - enable core clk */	ori	r4,r4,0x4020		/* dbling (no harm done on GA and GC */	mtiocr	r4			/* since bit not used) & DRC to latch */					/* data bus on rising edge of CAS */	/*----------------------------------------------------------------------- */	/* Clear XER. */	/*----------------------------------------------------------------------- */	mtxer	r0	/*----------------------------------------------------------------------- */	/* Invalidate i-cache and d-cache TAG arrays. */	/*----------------------------------------------------------------------- */	addi	r3,0,1024		/* 1/4 of I-cache size, half of D-cache */	addi	r4,0,1024		/* 1/4 of I-cache */..cloop:	iccci	0,r3	iccci	r4,r3	dccci	0,r3	addic.	r3,r3,-16		/* move back one cache line */	bne	..cloop			/* loop back to do rest until r3 = 0 */	/* */	/* initialize IOP480 so it can read 1 MB code area for SRAM spaces */	/* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */	/* */	/* first copy IOP480 register base address into r3 */	addis	r3,0,0x5000		/* IOP480 register base address hi *//*	ori	r3,r3,0x0000		/  IOP480 register base address lo */#ifdef CONFIG_ADCIOP	/* use r4 as the working variable */	/* turn on CS3 (LOCCTL.7) */	lwz	r4,0x84(r3)		/* LOCTL is at offset 0x84 */	andi.	r4,r4,0xff7f		/* make bit 7 = 0 -- CS3 mode */	stw	r4,0x84(r3)		/* LOCTL is at offset 0x84 */#endif#ifdef CONFIG_DASA_SIM	/* use r4 as the working variable */	/* turn on MA17 (LOCCTL.7) */	lwz	r4,0x84(r3)		/* LOCTL is at offset 0x84 */	ori	r4,r4,0x80		/* make bit 7 = 1 -- MA17 mode */	stw	r4,0x84(r3)		/* LOCTL is at offset 0x84 */#endif	/* turn on MA16..13 (LCS0BRD.12 = 0) */	lwz	r4,0x100(r3)		/* LCS0BRD is at offset 0x100 */	andi.	r4,r4,0xefff		/* make bit 12 = 0 */	stw	r4,0x100(r3)		/* LCS0BRD is at offset 0x100 */	/* make sure above stores all comlete before going on */	sync	/* last thing, set local init status done bit (DEVINIT.31) */	lwz	r4,0x80(r3)		/* DEVINIT is at offset 0x80 */	oris	r4,r4,0x8000		/* make bit 31 = 1 */	stw	r4,0x80(r3)		/* DEVINIT is at offset 0x80 */	/* clear all pending interrupts and disable all interrupts */	li	r4,-1			/* set p1 to 0xffffffff */	stw	r4,0x1b0(r3)		/* clear all pending interrupts */	stw	r4,0x1b8(r3)		/* clear all pending interrupts */	li	r4,0			/* set r4 to 0 */	stw	r4,0x1b4(r3)		/* disable all interrupts */	stw	r4,0x1bc(r3)		/* disable all interrupts */	/* make sure above stores all comlete before going on */	sync	/*----------------------------------------------------------------------- */	/* Enable two 128MB cachable regions. */	/*----------------------------------------------------------------------- */	addis	r1,r0,0x8000	addi	r1,r1,0x0001	mticcr	r1			/* instruction cache */	addis	r1,r0,0x0000	addi	r1,r1,0x0000	mtdccr	r1			/* data cache */	addis	r1,r0,CFG_INIT_RAM_ADDR@h	ori	r1,r1,CFG_INIT_SP_OFFSET	  /* set up the stack to SDRAM */	li	r0, 0			/* Make room for stack frame header and */	stwu	r0, -4(r1)		/* clear final stack frame so that	*/	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/	GET_GOT			/* initialize GOT access			*/	bl	board_init_f	/* run first part of init code (from Flash)	*/#endif	/* CONFIG_IOP480 *//*****************************************************************************/#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)	/*----------------------------------------------------------------------- */	/* Clear and set up some registers. */	/*----------------------------------------------------------------------- */	addi	r4,r0,0x0000	mtspr	sgr,r4	mtspr	dcwr,r4	mtesr	r4			/* clear Exception Syndrome Reg */	mttcr	r4			/* clear Timer Control Reg */	mtxer	r4			/* clear Fixed-Point Exception Reg */	mtevpr	r4			/* clear Exception Vector Prefix Reg */	addi	r4,r0,0x1000		/* set ME bit (Machine Exceptions) */	oris	r4,r4,0x0002		/* set CE bit (Critical Exceptions) */	mtmsr	r4			/* change MSR */	addi	r4,r0,(0xFFFF-0x10000)		/* set r4 to 0xFFFFFFFF (status in the */					/* dbsr is cleared by setting bits to 1) */	mtdbsr	r4			/* clear/reset the dbsr */	/*----------------------------------------------------------------------- */	/* Invalidate I and D caches. Enable I cache for defined memory regions */	/* to speed things up. Leave the D cache disabled for now. It will be */	/* enabled/left disabled later based on user selected menu options. */	/* Be aware that the I cache may be disabled later based on the menu */	/* options as well. See miscLib/main.c. */	/*----------------------------------------------------------------------- */	bl	invalidate_icache	bl	invalidate_dcache	/*----------------------------------------------------------------------- */	/* Enable two 128MB cachable regions. */	/*----------------------------------------------------------------------- */	addis	r4,r0,0x8000	addi	r4,r4,0x0001	mticcr	r4			/* instruction cache */	isync	addis	r4,r0,0x0000	addi	r4,r4,0x0000	mtdccr	r4			/* data cache */#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))	/*----------------------------------------------------------------------- */	/* Tune the speed and size for flash CS0  */	/*----------------------------------------------------------------------- */	bl	ext_bus_cntlr_init#endif#ifdef CONFIG_TAIHU	bl	ext_bus_cntlr_init#endif#if defined(CONFIG_405EP)	/*----------------------------------------------------------------------- */	/* DMA Status, clear to come up clean */	/*----------------------------------------------------------------------- */	addis	r3,r0, 0xFFFF	      /* Clear all existing DMA status */	ori	r3,r3, 0xFFFF	mtdcr	dmasr, r3	bl	ppc405ep_init	      /* do ppc405ep specific init */#endif /* CONFIG_405EP */#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)	/********************************************************************	 * Setup OCM - On Chip Memory	 *******************************************************************/	/* Setup OCM */	lis	r0, 0x7FFF	ori	r0, r0, 0xFFFF	mfdcr	r3, ocmiscntl		/* get instr-side IRAM config */	mfdcr	r4, ocmdscntl	/* get data-side IRAM config */	and	r3, r3, r0	/* disable data-side IRAM */	and	r4, r4, r0	/* disable data-side IRAM */	mtdcr	ocmiscntl, r3	/* set instr-side IRAM config */	mtdcr	ocmdscntl, r4	/* set data-side IRAM config */	isync	addis	r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */	mtdcr	ocmdsarc, r3	addis	r4, 0, 0xC000		/* OCM data area enabled */	mtdcr	ocmdscntl, r4	isync#endif	/*----------------------------------------------------------------------- */	/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */	/*----------------------------------------------------------------------- */#ifdef CFG_INIT_DCACHE_CS	/*----------------------------------------------------------------------- */	/* Memory Bank x (nothingness) initialization 1GB+64MEG */	/* used as temporary stack pointer for stage0  */	/*----------------------------------------------------------------------- */	li	r4,PBxAP	mtdcr	ebccfga,r4	lis	r4,0x0380	ori	r4,r4,0x0480	mtdcr	ebccfgd,r4	addi	r4,0,PBxCR	mtdcr	ebccfga,r4	lis	r4,0x400D	ori	r4,r4,0xa000	mtdcr	ebccfgd,r4	/* turn on data chache for this region */	lis	r4,0x0080	mtdccr	r4	/* set stack pointer and clear stack to known value */	lis	r1,CFG_INIT_RAM_ADDR@h	ori	r1,r1,CFG_INIT_SP_OFFSET@l	li	r4,2048			/* we store 2048 words to stack */	mtctr	r4	lis	r2,CFG_INIT_RAM_ADDR@h		/* we also clear data area */	ori	r2,r2,CFG_INIT_RAM_END@l	/* so cant copy value from r1 */	lis	r4,0xdead		/* we store 0xdeaddead in the stack */	ori	r4,r4,0xdead..stackloop:	stwu	r4,-4(r2)	bdnz	..stackloop	li	r0, 0			/* Make room for stack frame header and */	stwu	r0, -4(r1)		/* clear final stack frame so that	*/	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/	/*	 * Set up a dummy frame to store reset vector as return address.	 * this causes stack underflow to reset board.	 */	stwu	r1, -8(r1)		/* Save back chain and move SP */	addis	r0, 0, RESET_VECTOR@h	/* Address of reset vector */	ori	r0, r0, RESET_VECTOR@l	stwu	r1, -8(r1)		/* Save back chain and move SP */	stw	r0, +12(r1)		/* Save return addr (underflow vect) */#elif defined(CFG_TEMP_STACK_OCM) && \	(defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))	/*	 * Stack in OCM.	 */	/* Set up Stack at top of OCM */	lis	r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l	/* Set up a zeroized stack frame so that backtrace works right */	li	r0, 0	stwu	r0, -4(r1)	stwu	r0, -4(r1)	/*	 * Set up a dummy frame to store reset vector as return address.	 * this causes stack underflow to reset board.	 */	stwu	r1, -8(r1)		/* Save back chain and move SP */	lis	r0, RESET_VECTOR@h	/* Address of reset vector */	ori	r0, r0, RESET_VECTOR@l	stwu	r1, -8(r1)		/* Save back chain and move SP */	stw	r0, +12(r1)		/* Save return addr (underflow vect) */#endif /* CFG_INIT_DCACHE_CS */	/*----------------------------------------------------------------------- */	/* Initialize SDRAM Controller	*/	/*----------------------------------------------------------------------- */	bl	sdram_init	/*	 * Setup temporary stack pointer only for boards	 * that do not use SDRAM SPD I2C stuff since it	 * is already initialized to use DCACHE or OCM	 * stacks.	 */#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))	lis	r1, CFG_INIT_RAM_ADDR@h	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */	li	r0, 0			/* Make room for stack frame header and */	stwu	r0, -4(r1)		/* clear final stack frame so that	*/	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/	/*	 * Set up a dummy frame to store reset vector as return address.	 * this causes stack underflow to reset board.	 */	stwu	r1, -8(r1)		/* Save back chain and move SP */	lis	r0, RESET_VECTOR@h	/* Address of reset vector */	ori	r0, r0, RESET_VECTOR@l	stwu	r1, -8(r1)		/* Save back chain and move SP */	stw	r0, +12(r1)		/* Save return addr (underflow vect) */#endif /* !(CFG_INIT_DCACHE_CS	|| !CFG_TEM_STACK_OCM) */	GET_GOT			/* initialize GOT access			*/	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */	/* NEVER RETURNS! */	bl	board_init_f	/* run first part of init code (from Flash)	*/#endif	/* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */	/*----------------------------------------------------------------------- *//*****************************************************************************/	.globl	_start_of_vectors_start_of_vectors:#if 0/*TODO Fixup _start above so we can do this*//* Critical input. */	CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)#endif/* Machine check */	CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)/* Data Storage exception. */	STD_EXCEPTION(0x300, DataStorage, UnknownException)/* Instruction Storage exception. */	STD_EXCEPTION(0x400, InstStorage, UnknownException)/* External Interrupt exception. */	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)/* Alignment exception. */	. = 0x600Alignment:	EXCEPTION_PROLOG	mfspr	r4,DAR	stw	r4,_DAR(r21)	mfspr	r5,DSISR	stw	r5,_DSISR(r21)	addi	r3,r1,STACK_FRAME_OVERHEAD	li	r20,MSR_KERNEL	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */	lwz	r6,GOT(transfer_to_handler)	mtlr	r6	blrl.L_Alignment:	.long	AlignmentException - _start + EXC_OFF_SYS_RESET	.long	int_return - _start + EXC_OFF_SYS_RESET/* Program check exception */	. = 0x700ProgramCheck:	EXCEPTION_PROLOG	addi	r3,r1,STACK_FRAME_OVERHEAD	li	r20,MSR_KERNEL	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */	lwz	r6,GOT(transfer_to_handler)	mtlr	r6	blrl.L_ProgramCheck:	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET	.long	int_return - _start + EXC_OFF_SYS_RESET	/* No FPU on MPC8xx.  This exception is not supposed to happen.	*/	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)	/* I guess we could implement decrementer, and may have	 * to someday for timekeeping.	 */	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)	STD_EXCEPTION(0xc00, SystemCall, UnknownException)	STD_EXCEPTION(0xd00, SingleStep, UnknownException)	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)	/* On the MPC8xx, this is a software emulation interrupt.  It occurs	 * for all unimplemented and illegal instructions.	 */	STD_EXCEPTION(0x1000, PIT, PITException)	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)	STD_EXCEPTION(0x1500, Reserved5, UnknownException)	STD_EXCEPTION(0x1600, Reserved6, UnknownException)	STD_EXCEPTION(0x1700, Reserved7, UnknownException)	STD_EXCEPTION(0x1800, Reserved8, UnknownException)	STD_EXCEPTION(0x1900, Reserved9, UnknownException)	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)	CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )	.globl	_end_of_vectors_end_of_vectors:	. = 0x2100