andn		%g1, DTAG_MASK, %g1		! IEU1	cmp		%o0, %o3			! IEU1	Group	be,a,pn		%xcc, dflush1			! CTI	 sub		%o4, (4 << 5), %o4		! IEU0	(Group)	cmp		%o0, %g1			! IEU1	Group	andn		%g2, DTAG_MASK, %g2		! IEU0	be,a,pn		%xcc, dflush2			! CTI	 sub		%o4, (3 << 5), %o4		! IEU0	(Group)	cmp		%o0, %g2			! IEU1	Group	andn		%g3, DTAG_MASK, %g3		! IEU0	be,a,pn		%xcc, dflush3			! CTI	 sub		%o4, (2 << 5), %o4		! IEU0	(Group)	cmp		%o0, %g3			! IEU1	Group	be,a,pn		%xcc, dflush4			! CTI	 sub		%o4, (1 << 5), %o4		! IEU02:	cmp		%o4, %o2			! IEU1	Group	bne,pt		%xcc, 1b			! CTI	 nop						! IEU0	/* The I-cache does not snoop local stores so we	 * better flush that too when necessary.	 */	brnz,pt		%o1, __flush_icache_page	 sllx		%o0, 11, %o0	retl	 nopdflush1:stxa		%g0, [%o4] ASI_DCACHE_TAG	add		%o4, (1 << 5), %o4dflush2:stxa		%g0, [%o4] ASI_DCACHE_TAG	add		%o4, (1 << 5), %o4dflush3:stxa		%g0, [%o4] ASI_DCACHE_TAG	add		%o4, (1 << 5), %o4dflush4:stxa		%g0, [%o4] ASI_DCACHE_TAG	add		%o4, (1 << 5), %o4	membar		#Sync	ba,pt		%xcc, 2b	 nop	.align		32__prefill_dtlb:	rdpr		%pstate, %g7	wrpr		%g7, PSTATE_IE, %pstate	mov		TLB_TAG_ACCESS, %g1	stxa		%o0, [%g1] ASI_DMMU	stxa		%o1, [%g0] ASI_DTLB_DATA_IN	flush		%g6	retl	 wrpr		%g7, %pstate__prefill_itlb:	rdpr		%pstate, %g7	wrpr		%g7, PSTATE_IE, %pstate	mov		TLB_TAG_ACCESS, %g1	stxa		%o0, [%g1] ASI_IMMU	stxa		%o1, [%g0] ASI_ITLB_DATA_IN	flush		%g6	retl	 wrpr		%g7, %pstate	.globl		__update_mmu_cache__update_mmu_cache:	/* %o0=vma, %o1=address, %o2=pte */	ldub		[%g6 + AOFF_task_thread + AOFF_thread_fault_code], %o3	srlx		%o1, PAGE_SHIFT, %o1	ldx		[%o0 + 0x0], %o4		/* XXX vma->vm_mm */	brz,pn		%o3, 1f	 sllx		%o1, PAGE_SHIFT, %o0	ldx		[%o4 + AOFF_mm_context], %o5	andcc		%o3, FAULT_CODE_DTLB, %g0	mov		%o2, %o1	and		%o5, TAG_CONTEXT_BITS, %o5	bne,pt		%xcc, __prefill_dtlb	 or		%o0, %o5, %o0	ba,a,pt		%xcc, __prefill_itlb1:	retl	 nop#ifdef CONFIG_SMP	/* These are all called by the slaves of a cross call, at	 * trap level 1, with interrupts fully disabled.	 *	 * Register usage:	 *   %g5	mm->context	(all tlb flushes)	 *   %g1	address arg 1	(tlb page and range flushes)	 *   %g7	address arg 2	(tlb range flush only)	 *	 *   %g6	ivector table, don't touch	 *   %g2	scratch 1	 *   %g3	scratch 2	 *   %g4	scratch 3	 *	 * TODO: Make xcall TLB range flushes use the tricks above... -DaveM	 */	.align		32	.globl		xcall_flush_tlb_page, xcall_flush_tlb_mm, xcall_flush_tlb_rangexcall_flush_tlb_page:	mov		PRIMARY_CONTEXT, %g2	ldxa		[%g2] ASI_DMMU, %g3	stxa		%g5, [%g2] ASI_DMMU	stxa		%g0, [%g1] ASI_DMMU_DEMAP	stxa		%g0, [%g1] ASI_IMMU_DEMAP	stxa		%g3, [%g2] ASI_DMMU	retry	nopxcall_flush_tlb_mm:	mov		PRIMARY_CONTEXT, %g2	mov		0x40, %g4	ldxa		[%g2] ASI_DMMU, %g3	stxa		%g5, [%g2] ASI_DMMU	stxa		%g0, [%g4] ASI_DMMU_DEMAP	stxa		%g0, [%g4] ASI_IMMU_DEMAP	stxa		%g3, [%g2] ASI_DMMU	retryxcall_flush_tlb_range:	sethi		%hi(PAGE_SIZE - 1), %g2	or		%g2, %lo(PAGE_SIZE - 1), %g2	andn		%g1, %g2, %g1	andn		%g7, %g2, %g7	sub		%g7, %g1, %g3	add		%g2, 1, %g2	srlx		%g3, PAGE_SHIFT, %g4	cmp		%g4, 96	bgu,pn		%icc, xcall_flush_tlb_mm	 mov		PRIMARY_CONTEXT, %g4	ldxa		[%g4] ASI_DMMU, %g7	sub		%g3, %g2, %g3	stxa		%g5, [%g4] ASI_DMMU	nop	nop	nop1:	stxa		%g0, [%g1 + %g3] ASI_DMMU_DEMAP	stxa		%g0, [%g1 + %g3] ASI_IMMU_DEMAP	membar		#Sync	brnz,pt		%g3, 1b	 sub		%g3, %g2, %g3	stxa		%g7, [%g4] ASI_DMMU	retry	nop	nop	.globl		xcall_report_regsxcall_report_regs:	rdpr		%pstate, %g2	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate	rdpr		%pil, %g2	wrpr		%g0, 15, %pil	sethi		%hi(109f), %g7	b,pt		%xcc, etrap_irq109:	 or		%g7, %lo(109b), %g7	call		__show_regs	 add		%sp, STACK_BIAS + REGWIN_SZ, %o0	b,pt		%xcc, rtrap	 clr		%l6	.align		32	.globl		xcall_flush_dcache_page_cheetahxcall_flush_dcache_page_cheetah: /* %g1 == physical page address */	sethi		%hi(PAGE_SIZE), %g31:	subcc		%g3, (1 << 5), %g3	stxa		%g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE	bne,pt		%icc, 1b	 nop	membar		#Sync	retry	nop	.globl		xcall_flush_dcache_page_spitfirexcall_flush_dcache_page_spitfire: /* %g1 == physical page address				     %g7 == kernel page virtual address				     %g5 == (page->mapping != NULL)  */#if (L1DCACHE_SIZE > PAGE_SIZE)	srlx		%g1, (13 - 2), %g1	! Form tag comparitor	sethi		%hi(L1DCACHE_SIZE), %g3	! D$ size == 16K	sub		%g3, (1 << 5), %g3	! D$ linesize == 321:	ldxa		[%g3] ASI_DCACHE_TAG, %g2	andcc		%g2, 0x3, %g0	be,pn		%xcc, 2f	 andn		%g2, 0x3, %g2	cmp		%g2, %g1	bne,pt		%xcc, 2f	 nop	stxa		%g0, [%g3] ASI_DCACHE_TAG	membar		#Sync2:	cmp		%g3, 0	bne,pt		%xcc, 1b	 sub		%g3, (1 << 5), %g3	brz,pn		%g5, 2f#endif /* L1DCACHE_SIZE > PAGE_SIZE */	 sethi		%hi(PAGE_SIZE), %g31:	flush		%g7	subcc		%g3, (1 << 5), %g3	bne,pt		%icc, 1b	 add		%g7, (1 << 5), %g72:	retry	nop	nop	.globl		xcall_capturexcall_capture:	rdpr		%pstate, %g2	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate	rdpr		%pil, %g2	wrpr		%g0, 15, %pil	sethi		%hi(109f), %g7	b,pt		%xcc, etrap_irq109:	 or		%g7, %lo(109b), %g7	call		smp_penguin_jailcell	 nop	b,pt		%xcc, rtrap	 clr		%l6	.globl		xcall_promstopxcall_promstop:	rdpr		%pstate, %g2	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate	rdpr		%pil, %g2	wrpr		%g0, 15, %pil	sethi		%hi(109f), %g7	b,pt		%xcc, etrap_irq109:	 or		%g7, %lo(109b), %g7	flushw	call		prom_stopself	 nop	/* We should not return, just spin if we do... */1:	b,a,pt		%xcc, 1b	nop	.globl		xcall_receive_signalxcall_receive_signal:	rdpr		%pstate, %g2	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate	rdpr		%tstate, %g1	andcc		%g1, TSTATE_PRIV, %g0	/* If we did not trap from user space, just ignore. */	bne,pn		%xcc, 99f	 sethi		%hi(109f), %g7	b,pt		%xcc, etrap109:	 or		%g7, %lo(109b), %g7	b,pt		%xcc, rtrap	 clr		%l699:	retry	.dataerrata32_hwbug:	.xword	0	.text	/* These two are not performance critical... */	.globl		xcall_flush_tlb_allxcall_flush_tlb_all:	BRANCH_IF_CHEETAH(g2, g3, __cheetah_xcall_flush_tlb_all)__spitfire_xcall_flush_tlb_all:	/* Spitfire Errata #32 workaround. */	sethi		%hi(errata32_hwbug), %g4	stx		%g0, [%g4 + %lo(errata32_hwbug)]	clr		%g2	clr		%g31:	ldxa		[%g3] ASI_DTLB_DATA_ACCESS, %g4	and		%g4, _PAGE_L, %g5	brnz,pn		%g5, 2f	 mov		TLB_TAG_ACCESS, %g7	stxa		%g0, [%g7] ASI_DMMU	membar		#Sync	stxa		%g0, [%g3] ASI_DTLB_DATA_ACCESS	membar		#Sync	/* Spitfire Errata #32 workaround. */	sethi		%hi(errata32_hwbug), %g4	stx		%g0, [%g4 + %lo(errata32_hwbug)]2:	ldxa		[%g3] ASI_ITLB_DATA_ACCESS, %g4	and		%g4, _PAGE_L, %g5	brnz,pn		%g5, 2f	 mov		TLB_TAG_ACCESS, %g7	stxa		%g0, [%g7] ASI_IMMU	membar		#Sync	stxa		%g0, [%g3] ASI_ITLB_DATA_ACCESS	membar		#Sync	/* Spitfire Errata #32 workaround. */	sethi		%hi(errata32_hwbug), %g4	stx		%g0, [%g4 + %lo(errata32_hwbug)]2:	add		%g2, 1, %g2	cmp		%g2, SPITFIRE_HIGHEST_LOCKED_TLBENT	ble,pt		%icc, 1b	 sll		%g2, 3, %g3	flush		%g6	retry__cheetah_xcall_flush_tlb_all:	mov		0x80, %g2	stxa		%g0, [%g2] ASI_DMMU_DEMAP	stxa		%g0, [%g2] ASI_IMMU_DEMAP	retry	.globl		xcall_flush_cache_allxcall_flush_cache_all:	BRANCH_IF_CHEETAH(g2, g3, __cheetah_xcall_flush_cache_all)__spitfire_xcall_flush_cache_all:	sethi		%hi(16383), %g2	or		%g2, %lo(16383), %g2	clr		%g31:	stxa		%g0, [%g3] ASI_IC_TAG	membar		#Sync	add		%g3, 32, %g3	cmp		%g3, %g2	bleu,pt		%xcc, 1b	 nop	flush		%g6	retry	/* Cheetah's caches are fully coherent in the sense that	 * caches are flushed here.  We need to verify this and	 * really just not even send out the xcall at the top level.	 */__cheetah_xcall_flush_cache_all:	retry	.globl		xcall_call_functionxcall_call_function:	rdpr		%pstate, %g2	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate	rdpr		%pil, %g2	wrpr		%g0, 15, %pil	sethi		%hi(109f), %g7	b,pt		%xcc, etrap_irq109:	 or		%g7, %lo(109b), %g7	call		smp_call_function_client	 nop	b,pt		%xcc, rtrap	 clr		%l6#endif /* CONFIG_SMP */