?? cc88259.txt.txt
字號:
D_OUT : out STD_LOGIC_VECTOR (7 downto 0);
IRR_N : out STD_LOGIC_VECTOR (7 downto 0);
ISR_O : out STD_LOGIC_VECTOR (7 downto 0);
FREEZE : in STD_LOGIC;
ISR_ACCEPT: in std_logic;
LEVEL : in STD_LOGIC;
READ : in STD_LOGIC;
RESET : in STD_LOGIC;
MASK : in STD_LOGIC
);
end PR_CELL8;
architecture SCHEMATIC of PR_CELL8 is
component Prior_cell
port(
FREEZE : in std_logic;
IMR : in std_logic;
IRR_WT : in std_logic;
IR_EN : in std_logic;
ISR_ACCEPT : in std_logic;
ISR_CLR : in std_logic;
LEVEL : in std_logic;
MASK : in std_logic;
READ : in std_logic;
RESET : in std_logic;
D_OUT : out std_logic;
IRR_N : out std_logic;
ISR_O : out std_logic);
end component;
begin
--COMPONENT INSTANCES
PR_CELL_G: for I in 0 to 7 generate
H1 : PRIOR_CELL port map(
IMR => IMR(I),
IR_EN => IR(I),
ISR_CLR => ISR_CLR(I),
LEVEL => LEVEL,
FREEZE => FREEZE,
READ => READ,
RESET => RESET,
ISR_ACCEPT => ISR_ACCEPT,
MASK => MASK,
D_OUT => D_OUT(I),
IRR_N => IRR_N(I),
ISR_O => ISR_O(I),
IRR_WT => IRR_WT(I)
);
end generate;
end SCHEMATIC;
------------------------------------------------------------------------------------
-- CMP_A_ISR --------------------------------------------------------------------
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity CMP_A_ISR is
port (
ISR_A: in STD_LOGIC_VECTOR (7 downto 0);
ISR_W: out STD_LOGIC_VECTOR (7 downto 0)
);
end CMP_A_ISR;
architecture CMP_A_ISR_arch of CMP_A_ISR is
begin
ISR_W <= "00000001" when ( ISR_A(0)='1' ) else
"00000010" when ( ISR_A(1)='1' ) else
"00000100" when ( ISR_A(2)='1' ) else
"00001000" when ( ISR_A(3)='1' ) else
"00010000" when ( ISR_A(4)='1' ) else
"00100000" when ( ISR_A(5)='1' ) else
"01000000" when ( ISR_A(6)='1' ) else
"10000000" when ( ISR_A(7)='1' ) else
"00000000";
end CMP_A_ISR_arch;
------------------------------------------------------------------------------------
-- IRR_W ------------------------------------------------------------------------
------------------------------------------------------------------------------------
library IEEE;use IEEE.std_logic_1164.all;
entity IRR_W is
port (
ISR_M: in STD_LOGIC_VECTOR (7 downto 0);
IRR_M: in STD_LOGIC_VECTOR (7 downto 0);
IRR_W: out STD_LOGIC_VECTOR (7 downto 0);
IR_WORK: out std_logic;
ISR_ACCEPT: in STD_LOGIC;
RESET: in STD_LOGIC
);
end IRR_W;
architecture IRR_W_arch of IRR_W is
component D_LATCH8
port(
GATE : in std_logic;
I : in std_logic_vector(7 downto 0);
RESET : in std_logic;
O : out std_logic_vector(7 downto 0));
end component;
signal IRR_T: STD_LOGIC_VECTOR (7 downto 0);
signal IRR_PR: STD_LOGIC_VECTOR (7 downto 0);
begin
IRR_T(0) <= IRR_M(0);
IRR_T(1) <= IRR_M(1) and (not IRR_T(0)) and (not ISR_M(0));
IRR_T(2) <= IRR_M(2) and (not IRR_T(0)) and (not ISR_M(0))
and (not IRR_T(1)) and (not ISR_M(1));
IRR_T(3) <= IRR_M(3) and (not IRR_T(0)) and (not ISR_M(0))
and (not IRR_T(1)) and (not ISR_M(1))
and (not IRR_T(2)) and (not ISR_M(2)) ;
IRR_T(4) <= IRR_M(4) and (not IRR_T(0)) and (not ISR_M(0))
and (not IRR_T(1)) and (not ISR_M(1))
and (not IRR_T(2)) and (not ISR_M(2))
and (not IRR_T(3)) and (not ISR_M(3)) ;
IRR_T(5) <= IRR_M(5) and (not IRR_T(0)) and (not ISR_M(0))
and (not IRR_T(1)) and (not ISR_M(1))
and (not IRR_T(2)) and (not ISR_M(2))
and (not IRR_T(3)) and (not ISR_M(3))
and (not IRR_T(4)) and (not ISR_M(4)) ;
IRR_T(6) <= IRR_M(6) and (not IRR_T(0)) and (not ISR_M(0))
and (not IRR_T(1)) and (not ISR_M(1))
and (not IRR_T(2)) and (not ISR_M(2))
and (not IRR_T(3)) and (not ISR_M(3))
and (not IRR_T(4)) and (not ISR_M(4))
and (not IRR_T(5)) and (not ISR_M(5)) ;
IRR_T(7) <= IRR_M(7) and (not IRR_T(0)) and (not ISR_M(0))
and (not IRR_T(1)) and (not ISR_M(1))
and (not IRR_T(2)) and (not ISR_M(2))
and (not IRR_T(3)) and (not ISR_M(3))
and (not IRR_T(4)) and (not ISR_M(4))
and (not IRR_T(5)) and (not ISR_M(5))
and (not IRR_T(6)) and (not ISR_M(6)) ;
SET_GATE: D_LATCH8 port map (
I => IRR_T,
GATE => ISR_ACCEPT,
RESET => RESET,
O => IRR_PR);
IR_WORK <= IRR_PR(0) or IRR_PR(1) or IRR_PR(2) or IRR_PR(3) or
IRR_PR(4) or IRR_PR(5) or IRR_PR(6) or IRR_PR(7);
IRR_W <= IRR_PR;
end IRR_W_arch;
------------------------------------------------------------------------------------
-- ISR_PR -----------------------------------------------------------------------
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ISR_PR is
port (
ISR_W: in STD_LOGIC_VECTOR (7 downto 0);
IPR_O: in STD_LOGIC_VECTOR (2 downto 0);
EOI_N: in STD_LOGIC_VECTOR (2 downto 0);
ISR_CLR: out STD_LOGIC_VECTOR (7 downto 0);
EOI_2, EOI_4, EOI_5: in std_logic;
IPR_SET: out STD_LOGIC_VECTOR (2 downto 0)
);
end ISR_PR;
architecture ISR_PR_arch of ISR_PR is
component BRLSHFT8_L
port(
I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
O : out std_logic_vector(7 downto 0));
end component;
signal ISR_CLR_A, ISR_CLR_B: std_logic_vector(7 downto 0);
begin
ROTATE: BRLSHFT8_L port map (
I => ISR_W,
S => IPR_O,
O => ISR_CLR_A);
ISR_CLR_B <= "00000001" when ( EOI_N="000" ) else
"00000010" when ( EOI_N="001" ) else
"00000100" when ( EOI_N="010" ) else
"00001000" when ( EOI_N="011" ) else
"00010000" when ( EOI_N="100" ) else
"00100000" when ( EOI_N="101" ) else
"01000000" when ( EOI_N="110" ) else
"10000000" when ( EOI_N="111" ) else
"00000000";
ISR_CLR <= ISR_CLR_B when ( (EOI_2 or EOI_4) = '1') else ISR_CLR_A;
IPR_SET <= "111" when ( ( EOI_N="110" and ( (EOI_5 or EOI_4) = '1') ) or ISR_CLR_A(6)='1' ) else
"000" when ( ( EOI_N="111" and ( (EOI_5 or EOI_4) = '1') ) or ISR_CLR_A(7)='1' ) else
"001" when ( ( EOI_N="000" and ( (EOI_5 or EOI_4) = '1') ) or ISR_CLR_A(0)='1' ) else
"010" when ( ( EOI_N="001" and ( (EOI_5 or EOI_4) = '1') ) or ISR_CLR_A(1)='1' ) else
"011" when ( ( EOI_N="010" and ( (EOI_5 or EOI_4) = '1') ) or ISR_CLR_A(2)='1' ) else
"100" when ( ( EOI_N="011" and ( (EOI_5 or EOI_4) = '1') ) or ISR_CLR_A(3)='1' ) else
"101" when ( ( EOI_N="100" and ( (EOI_5 or EOI_4) = '1') ) or ISR_CLR_A(4)='1' ) else
"110" when ( ( EOI_N="101" and ( (EOI_5 or EOI_4) = '1') ) or ISR_CLR_A(5)='1' ) else
"111" ;
end ISR_PR_arch;
------------------------------------------------------------------------------------
-- ISR_SET ----------------------------------------------------------------------
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ISR_SET is
port (
IRR_W: in STD_LOGIC_VECTOR (7 downto 0);
IRR_WP_OUT: out STD_LOGIC_VECTOR (7 downto 0);
IPR: in STD_LOGIC_VECTOR (2 downto 0);
IR_NR_WORK: out STD_LOGIC_VECTOR (2 downto 0)
);
end ISR_SET;
architecture ISR_SET_arch of ISR_SET is
component BRLSHFT8_L
port(
I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
O : out std_logic_vector(7 downto 0));
end component;
signal IRR_WP: STD_LOGIC_VECTOR (7 downto 0);
signal TEMP_IRR_WP: STD_LOGIC;
begin
ROTATE: BRLSHFT8_L port map (
I => IRR_W,
S => IPR,
O => IRR_WP);
IRR_WP_OUT <= IRR_WP;
TEMP_IRR_WP <= not (IRR_WP(0) or IRR_WP(1) or IRR_WP(2) or IRR_WP(3)
or IRR_WP(4) or IRR_WP(5) or IRR_WP(6) or IRR_WP(7));
IR_NR_WORK(0) <= IRR_WP(1) or IRR_WP(3) or IRR_WP(5) or IRR_WP(7) or TEMP_IRR_WP;
IR_NR_WORK(1) <= IRR_WP(2) or IRR_WP(3) or IRR_WP(6) or IRR_WP(7) or TEMP_IRR_WP;
IR_NR_WORK(2) <= IRR_WP(4) or IRR_WP(5) or IRR_WP(6) or IRR_WP(7) or TEMP_IRR_WP;
end ISR_SET_arch;
------------------------------------------------------------------------------------
-- IPR_RES ----------------------------------------------------------------------
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity IPR_RES is
port(
EOI_1 : in STD_LOGIC;
EOI_2 : in STD_LOGIC;
EOI_3 : in STD_LOGIC;
EOI_4 : in STD_LOGIC;
EOI_5 : in STD_LOGIC;
N_WR : in STD_LOGIC;
RESET : in STD_LOGIC;
EOI_N : in STD_LOGIC_VECTOR(2 downto 0);
ISR_A : in STD_LOGIC_VECTOR(7 downto 0);
IPR : out STD_LOGIC_VECTOR(2 downto 0);
ISR_CLR : out STD_LOGIC_VECTOR(7 downto 0)
);
end IPR_RES;
architecture IPR_RES of IPR_RES is
---- Component declarations -----
component cmp_a_isr
port (
ISR_A : in STD_LOGIC_VECTOR(7 downto 0);
ISR_W : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component fdcex3
port (
C : in STD_LOGIC;
CE : in STD_LOGIC;
CLR : in STD_LOGIC;
I : in STD_LOGIC_VECTOR(2 downto 0);
O : out STD_LOGIC_VECTOR(2 downto 0)
);
end component;
component fdcex8
port (
C : in STD_LOGIC;
CE : in STD_LOGIC;
CLR : in STD_LOGIC;
I : in STD_LOGIC_VECTOR(7 downto 0);
O : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component isr_pr
port (
EOI_2 : in STD_LOGIC;
EOI_4 : in STD_LOGIC;
EOI_5 : in STD_LOGIC;
EOI_N : in STD_LOGIC_VECTOR(2 downto 0);
IPR_O : in STD_LOGIC_VECTOR(2 downto 0);
ISR_W : in STD_LOGIC_VECTOR(7 downto 0);
IPR_SET : out STD_LOGIC_VECTOR(2 downto 0);
ISR_CLR : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component or2
port (
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic
);
end component;
component or3
port (
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
O : out STD_LOGIC
);
end component;
component or4
port (
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
O : out STD_LOGIC
);
end component;
component or8
port (
I : in STD_LOGIC_VECTOR(7 downto 0);
O : out STD_LOGIC
);
end component;
signal CLR_ISR_CLR : STD_LOGIC;
signal EOI_P : STD_LOGIC;
signal IPR_O : STD_LOGIC_VECTOR (2 downto 0);
signal IPR_SET : STD_LOGIC_VECTOR (2 downto 0);
signal ISR_CLR_ASS : STD_LOGIC_VECTOR (7 downto 0);
signal ISR_CLR_SET : STD_LOGIC_VECTOR (7 downto 0);
signal ISR_W : STD_LOGIC_VECTOR (7 downto 0);
signal WR_IPR : STD_LOGIC;
signal NET293 : std_logic;
begin
---- Component instantiations ----
U0 : cmp_a_isr
port map(
ISR_A => ISR_A,
ISR_W => ISR_W
);
U1 : isr_pr
port map(
EOI_2 => EOI_2,
EOI_4 => EOI_4,
EOI_5 => EOI_5,
EOI_N => EOI_N,
IPR_O => IPR_O,
IPR_SET => IPR_SET,
ISR_CLR => ISR_CLR_SET,
ISR_W => ISR_W
);
U2 : fdcex8
port map(
C => N_WR,
CE => EOI_P,
CLR => CLR_ISR_CLR,
I => ISR_CLR_SET,
O => ISR_CLR_ASS
);
U3 : or4
port map(
I1 => EOI_1,
I2 => EOI_3,
I3 => EOI_2,
I4 => EOI_4,
O => EOI_P
);
U4 : or2
port map(
I1 => RESET,
I2 => NET293,
O => CLR_ISR_CLR
);
U5 : or8
port map(
I => ISR_CLR_ASS,
O => NET293
);
U6 : or3
port map(
I0 => EOI_3,
I1 => EOI_4,
I2 => EOI_5,
O => WR_IPR
);
U7 : fdcex3
port map(
C => N_WR,
CE => WR_IPR,
CLR => RESET,
I => IPR_SET,
O => IPR_O
);
---- Terminal assignment ----
-- Output buffer terminals
IPR <= IPR_O;
ISR_CLR <= ISR_CLR_ASS;
end IPR_RES;
------------------------------------------------------------------------------------
-- CONTROLL ---------------------------------------------------------------------
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity Controll is
port(
EOI_1 : in STD_LOGIC;
EOI_2 : in STD_LOGIC;
EOI_3 : in STD_LOGIC;
EOI_4 : in STD_LOGIC;
EOI_5 : in STD_LOGIC;
FREEZE : in STD_LOGIC;
ISR_ACCEPT : in STD_LOGIC;
LEVEL : in STD_LOGIC;
MASK : in STD_LOGIC;
N_WR : in STD_LOGIC;
READ : in STD_LOGIC;
RESET : in STD_LOGIC;
EOI_N : in STD_LOGIC_VECTOR(2 downto 0);
IMR : in STD_LOGIC_VECTOR(7 downto 0);
IR : in STD_LOGIC_VECTOR(7 downto 0);
IR_WORK : out STD_LOGIC;
IR_NR_WORK : out STD_LOGIC_VECTOR(2 downto 0);
R_OUT : out STD_LOGIC_VECTOR(7 downto 0)
);
end Controll;
architecture Controll of Controll is
---- Component declarations -----
component brlshft8_r
port (
I : in STD_LOGIC_VECTOR(7 downto 0);
S : in STD_LOGIC_VECTOR(2 downto 0);
O : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component ipr_res
port (
EOI_1 : in STD_LOGIC;
EOI_2 : in STD_LOGIC;
EOI_3 : in STD_LOGIC;
EOI_4 : in STD_LOGIC;
EOI_5 : in STD_LOGIC;
EOI_N : in STD_LOGIC_VECTOR(2 downto 0);
ISR_A : in STD_LOGIC_VECTOR(7 downto 0);
N_WR : in STD_LOGIC;
RESET : in STD_LOGIC;
IPR : out STD_LOGIC_VECTOR(2 downto 0);
ISR_CLR : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component irr_w
port (
IRR_M : in STD_LOGIC_VECTOR(7 downto 0);
ISR_ACCEPT : in STD_LOGIC;
ISR_M : in STD_LOGIC_VECTOR(7 downto 0);
RESET : in STD_LOGIC;
IRR_W : out STD_LOGIC_VECTOR(7 downto 0);
IR_WORK : out STD_LOGIC
);
end component;
component isr_set
port (
IPR : in STD_LOGIC_VECTOR(2 downto 0);
IRR_W : in STD_LOGIC_VECTOR(7 downto 0);
IRR_WP_OUT : out STD_LOGIC_VECTOR(7 downto 0);
IR_NR_WORK : out STD_LOGIC_VECTOR(2 downto 0)
);
end component;
component pr_cell8
port (
FREEZE : in STD_LOGIC;
IMR : in STD_LOGIC_VECTOR(7 downto 0);
IR : in STD_LOGIC_VECTOR(7 downto 0);
IRR_WT : in STD_LOGIC_VECTOR(7 downto 0);
ISR_ACCEPT : in STD_LOGIC;
ISR_CLR : in STD_LOGIC_VECTOR(7 downto 0);
LEVEL : in STD_LOGIC;
MASK : in STD_LOGIC;
READ : in STD_LOGIC;
RESET : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR(7 downto 0);
IRR_N : out STD_LOGIC_VECTOR(7 downto 0);
ISR_O : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
signal IPR : STD_LOGIC_VECTOR (2 downto 0);
signal IRR_A : STD_LOGIC_VECTOR (7 downto 0);
signal IRR_O : STD_LOGIC_VECTOR (7 downto 0);
signal IRR_WP : STD_LOGIC_VECTOR (7 downto 0);
signal IR_NR : STD_LOGIC_VECTOR (2 downto 0);
signal IR_WORK_A : STD_LOGIC;
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