?? omap.h
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#ifndef _OMAPH_
#define _OMAPH_
////////////////////////////////////////////////////////////////////////////////
//
// Copyright 2004 by Texas Instruments Incorporated. All rights reserved.
// Property of Texas Instruments Incorporated. Restricted rights to use,
// duplicate or disclose this code are granted through contract.
//
////////////////////////////////////////////////////////////////////////////////
//
// Common definitions for the OMAP CPU's and EVM's.
//
////////////////////////////////////////////////////////////////////////////////
//
//MACROS
//
#define READ_REGISTER_ULONG( reg ) (*(volatile unsigned long *)(reg))
#define WRITE_REGISTER_ULONG( reg, val ) (*(volatile unsigned long *)(reg)) = ((unsigned long)val)
#define READ_REGISTER_USHORT( reg ) (*(unsigned short *)(reg))
#define WRITE_REGISTER_USHORT( reg, val ) (*(volatile unsigned short *)(reg)) = ((unsigned short)val)
#define READ_REGISTER_UCHAR( reg ) (*(volatile unsigned char *)(reg))
#define WRITE_REGISTER_UCHAR( reg, val ) (*(volatile unsigned char *)(reg)) = ((unsigned char)val)
//
// Generic masks.
//
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define N1KB 0x00000400 // 1KB block
#define N2KB 0x00000800 // 2KB block
#define N4KB 0x00001000 // 4KB block
#define N16KB 0x00004000 // 16KB block
#define N32KB 0x00008000 // 32KB block
#define N64KB 0x00010000 // 64KB block
#define N128KB 0x00020000 // 128KB block
#define N1MB 0x00100000 // 1MB block
#define N2MB 0x00200000 // 2MB block
#define N4MB 0x00400000 // 4MB block
#define N8MB 0x00800000 // 8MB block
#define N16MB 0x01000000 // 16MB block
#define N32MB 0x02000000 // 32MB block
#define N64MB 0x04000000 // 64MB block
// NAND Flash Controller Registers and Bits
#define NFC_BASE 0xFFFBCC00
#define pNFC_BASE *(volatile ULONG *) (0xFFFBCC00)
#define pNFC_REVISION *(volatile ULONG *) (0x00 + NFC_BASE)
#define pNFC_ACCESS *(volatile ULONG *) (0x04 + NFC_BASE)
#define pNFC_ADDR_SRC *(volatile ULONG *) (0x08 + NFC_BASE)
#define pNFC_CTRL *(volatile ULONG *) (0x10 + NFC_BASE)
#define pNFC_MASK *(volatile ULONG *) (0x14 + NFC_BASE)
#define pNFC_STATUS *(volatile ULONG *) (0x18 + NFC_BASE)
#define pNFC_READY *(volatile ULONG *) (0x1C + NFC_BASE)
#define pNFC_COMMAND *(volatile ULONG *) (0x20 + NFC_BASE)
#define pNFC_COMMAND_SEC *(volatile ULONG *) (0x24 + NFC_BASE)
#define pNFC_ECC_SELECT *(volatile ULONG *) (0x28 + NFC_BASE)
#define pNFC_ECC_1 *(volatile ULONG *) (0x2C + NFC_BASE)
#define pNFC_ECC_2 *(volatile ULONG *) (0x30 + NFC_BASE)
#define pNFC_ECC_3 *(volatile ULONG *) (0x34 + NFC_BASE)
#define pNFC_ECC_4 *(volatile ULONG *) (0x38 + NFC_BASE)
#define pNFC_ECC_5 *(volatile ULONG *) (0x3C + NFC_BASE)
#define pNFC_ECC_6 *(volatile ULONG *) (0x40 + NFC_BASE)
#define pNFC_ECC_7 *(volatile ULONG *) (0x44 + NFC_BASE)
#define pNFC_ECC_8 *(volatile ULONG *) (0x48 + NFC_BASE)
#define pNFC_ECC_9 *(volatile ULONG *) (0x4C + NFC_BASE)
#define pNFC_RESET *(volatile ULONG *) (0x50 + NFC_BASE)
#define pNFC_FIFO *(volatile ULONG *) (0x54 + NFC_BASE)
#define pNFC_FIFOCTRL *(volatile ULONG *) (0x58 + NFC_BASE)
#define pNFC_PSC_CLK *(volatile ULONG *) (0x5C + NFC_BASE)
#define pNFC_SYSTEST *(volatile ULONG *) (0x60 + NFC_BASE)
#define pNFC_SYSCFG *(volatile ULONG *) (0x64 + NFC_BASE)
#define pNFC_SYSSTATUS *(volatile ULONG *) (0x68 + NFC_BASE)
#define pNFC_FIFOTEST1 *(volatile ULONG *) (0x6C + NFC_BASE)
#define pNFC_FIFOTEST2 *(volatile ULONG *) (0x70 + NFC_BASE)
#define pNFC_FIFOTEST3 *(volatile ULONG *) (0x74 + NFC_BASE)
#define pNFC_FIFOTEST4 *(volatile ULONG *) (0x78 + NFC_BASE)
//Bits
#define NFC_WP 0x00000080
#define NFC_RDYBSY 0x00000040
#define NFC_PL3PF 0x00000010
#define NFC_PL2PF 0x00000008
#define NFC_PL1PF 0x00000004
#define NFC_PL0PF 0x00000002
#define NFC_PRG_ERASE 0x00000001
///////////////////////////////////////////////////////////////////////////////
// Memory Map Information.
///////////////////////////////////////////////////////////////////////////////
#define CS0_BASE 0x00000000 // Slow Memory (Flash, Asynch RAM)
#define CS1_BASE 0x04000000 // Slow Memory (Flash, Asynch RAM)
#define CS2_BASE 0x08000000 // Slow Memory (Flash, Asynch RAM)
#define CS3_BASE 0x0C000000 // Slow Memory (Flash, Asynch RAM)
#define CS4_BASE 0x10000000 // Fast Memory (SDRAM)
#define CS6_BASE 0x20000000 // Internal SRAM.
#define RAM_BASE CS4_BASE // Default SDRAM base address
#define RAM_SIZE N32MB // Default SDRAM size in bytes
// Memory space conversion.
#define KSEG_MASK 0xe0000000 // "111", region mask.
#define PHYSICAL_MASK 0x1fffffff // Inverse of KSEG_MASK.
#define CACHED 0x80000000 // "100", 512MB region of cached memory.
#define KSEG0_MASK CACHED
#define UNCACHED 0xa0000000 // "101", 512MB region of uncached memory.
#define KSEG1_MASK UNCACHED
#define INTREG_CONVERT 0x0bffffff // Internal register conversion constant.
#define INV_INTREG_CONVERT 0xf4000000 // Inverse of INTREG_CONVERT.
#define PCICONF_CONVERT 0x0befffff // PCI configuration register conversion constant.
#define INV_PCICONF_CONVERT 0xf4100000 // Inverse of PCICONF_CONVERT.
#define HEPLD_CONVERT 0x02600000 // Helen EPLD conversion constant.
#define ADDR_TBL_BLOCK_MASK_64M 0x03ffffff // Block size mask of the address table entry for 64MB.
#define ADDR_TBL_RSHIFT_MASK_64M 0x70000000 // Right shift operand mask for 64MB.
#define ADDR_TBL_LSHIFT_MASK_64M 0x1c000000 // Left shift operand mask for 64MB.
#define ADDR_TBL_BLOCK_MASK_32M 0x01ffffff // Block size mask of the address table entry for 32MB.
#define ADDR_TBL_RSHIFT_MASK_32M 0x78000000 // Right shift operand mask for 32MB.
#define ADDR_TBL_LSHIFT_MASK_32M 0x1e000000 // Left shift operand mask for 32MB.
#define ADDR_TBL_BLOCK_MASK_16M 0x00ffffff // Block size mask of the address table entry for 16MB.
#define ADDR_TBL_RSHIFT_MASK_16M 0x7c000000 // Right shift operand mask for 16MB.
#define ADDR_TBL_LSHIFT_MASK_16M 0x1f000000 // Left shift operand mask for 16MB.
///////////////////////////////////////////////////////////////////////////////
// ARM925T
///////////////////////////////////////////////////////////////////////////////
// ARM mode register.
#define USER_MODE 0x10 // User mode.
#define FIQ_MODE 0x11 // FIQ mode.
#define IRQ_MODE 0x12 // IRQ mode.
#define SVC_MODE 0x13 // Supervisor mode.
#define ABORT_MODE 0x17 // Abort mode.
#define UDF_MODE 0x1b // Undefined mode.
#define SYS_MODE 0x1f // System mode.
#define MODE_CLEAR 0x1f // Mode clear.
#define FIQ_DISABLE BIT6 // When set (1) disables FIQ's.
#define IRQ_DISABLE BIT7 // When set (1) disables IRQ's.
#define ENABLE_ICACHE 0x1272 // Turn on ICache
#define DISABLE_ICACHE 0x0272 // Turn off ICache
// Page table C and B bit constants for OEMARMCacheMode.
#define ARM_NOBITS 0x00000000
#define ARM_CBIT BIT3
#define ARM_BBIT BIT2
#define ARM_CBBITS (BIT3|BIT2)
// CP15_CTL register bit field masks for Rd.
#define CP15_CTL_MMU_ENABLE BIT0
#define CP15_CTL_ALIGN_FAULT_ENABLE BIT1
#define CP15_CTL_DATA_CACHE_ENABLE BIT2
#define CP15_CTL_WRITE_BUFFER_ENABLE BIT3
#define CP15_CTL_RESERVED0 (BIT4|BIT5|BIT6)
#define CP15_CTL_BIG_ENDIAN_ENABLE BIT7
#define CP15_CTL_SYSTEM_PROTECTION BIT8
#define CP15_CTL_ROM_PROTECTION BIT9
#define CP15_CTL_RESERVED1 (BIT10|BIT11)
#define CP15_CTL_INST_CACHE_ENABLE BIT12
#define CP15_CTL_HIGH_VECTOR_ENABLE BIT13
// CP15_CFG register bit field masks for Rd.
#define CP15_CFG_LOCK_ENABLE BIT0 // Enable lock on SWAP.
#define CP15_CFG_TRANS_MODE_ENABLE BIT1 // Line loads hide line copy-backs.
#define CP15_CFG_DCACHE_CLFL_ENTRY_MODE BIT2 // Use D[31] to select dcache entry.
#define CP15_CFG_WRITE_BUFFER_CONFIG (BIT3|BIT4)
#define CP15_CFG_ARM915T_NOT_WINCE BIT5 // Select ARM915T (vs. WinCE).
#define CP15_CFG_RESERVED0 BIT6
#define CP15_CFG_ICACHE_STREAM_DISABLE BIT7 // Icache streaming disabled.
///////////////////////////////////////////////////////////////////////////////
// Shared Memory Interface (SMIF) register addresses.
///////////////////////////////////////////////////////////////////////////////
#define SMIF_BASE 0xfffecc00
#define IMIF_PRIORITY (SMIF_BASE+0x0) // IMIF priority.
#define EMIF_SLOW_PRIORITY (SMIF_BASE+0x4) // Slow EMIF priority.
#define EMIF_FAST_PRIORITY (SMIF_BASE+0x8) // Fast EMIF priority.
#define MIF_CONFIG_REG (SMIF_BASE+0xc) // Slow EMIF Configuration.
#define EMIF_SLOW_CS0_CONFIG (SMIF_BASE+0x10) // Slow chip select 0 configuration.
#define EMIF_SLOW_CS1_CONFIG (SMIF_BASE+0x14) // Slow chip select 1 configuration.
#define EMIF_SLOW_CS2_CONFIG (SMIF_BASE+0x18) // Slow chip select 2 configuration.
#define EMIF_SLOW_CS3_CONFIG (SMIF_BASE+0x1c) // Slow chip select 3 configuration.
#define EMIF_FAST_SD_CONFIG (SMIF_BASE+0x20) // SDRAM refresh, type, freq.
#define EMIF_FAST_SD_MRS (SMIF_BASE+0x24) // SDRAM CAS latency, burst length.
#define EMIF_TIMEOUT1 (SMIF_BASE+0x28) // Priority timeouts: LB, DMA
#define EMIF_TIMEOUT2 (SMIF_BASE+0x2C) // Priority timeouts: DSP, LCD
#define EMIF_TIMEOUT3 (SMIF_BASE+0x30) // Priority timeouts: HSAB
#define EMIF_ENDIANISM (SMIF_BASE+0x34) // Enable DSP Endian Conversion
#define EMIF_FAST_SD_CONFIG2 (SMIF_BASE+0x3C) // EMIF Fast Interface SDRAM second configuration register
#define EMIF_CONFIGDYNAMICWAITSTATE (SMIF_BASE+0x40) // Configure dynamic wait state for each CS
// EMIFF SDRAM Configuration Register
#define ARE_BITS (BIT3|BIT2) // Auto Refresh Bits
#define PWD_BIT BIT26 // Power Down
#define DISABLE_SDRAM_CLK BIT27 // SDRAM Clock
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