?? omap.h
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#define SELF_REFRESH BIT0 // Self Refresh
// EMIFF SDRAM Configuration Register
#define SD_SLFR_WHEN_RST BIT1 // Puts the SDRAM into self-refresh mode in case of a global reset.
#define SD_SLFR_WHEN_STBY BIT0 // Puts the SDRAM into the self-refresh mode in case of a clock cut request by the clock manager.
// EMIFS_GLB_CONFIG Register
#define PDE_BIT BIT3 // Power Down Enable
#define PWD_EN BIT2 // IMIF power down enable
#define BM BIT1 // MPU Boot Mode
///////////////////////////////////////////////////////////////////////////////
// CLKM module.
///////////////////////////////////////////////////////////////////////////////
#define CLKM1_BASE 0xfffece00 // ARM clock module.
#define CLKM_CKCTL (CLKM1_BASE+0x00) // Clock divisors.
#define CLKM_IDLECT1 (CLKM1_BASE+0x04) // Clock domain control.
#define CLKM_IDLECT2 (CLKM1_BASE+0x08) // Clock domain control.
#define CLKM_EWUPCT (CLKM1_BASE+0x0c) // External wakeup control.
#define CLKM_RSTCT1 (CLKM1_BASE+0x10) // Software CPU reset.
#define CLKM_RSTCT2 (CLKM1_BASE+0x14) // Peripheral reset.
#define CLKM_SYSST (CLKM1_BASE+0x18) // System state.
#define CLKM_CKOUT1 (CLKM1_BASE+0x1c) // Clock out control.
#define CLKM2_BASE 0xe1008000 // DSP clock module.
#define CLKM2_CKCTL (CLKM2_BASE+0x00) // Clock divisors.
#define CLKM2_IDLECT1 (CLKM2_BASE+0x04) // Clock domain control.
#define CLKM2_IDLECT2 (CLKM2_BASE+0x08) // Clock domain control.
#define CLKM2_EWUPCT (CLKM2_BASE+0x0c) // External wakeup control.
#define CLKM2_RSTCT1 (CLKM2_BASE+0x10) // Software CPU reset.
#define CLKM2_RSTCT2 (CLKM2_BASE+0x14) // Peripheral reset.
#define CLKM2_SYSST (CLKM2_BASE+0x18) // System state.
#define CLKM2_CKOUT1 (CLKM2_BASE+0x1c) // Clock out control.
#define CLKM_DPLL1CTL 0xfffecf00 // DPLL1 control register.
#define CLKM_DPLL2CTL 0xfffed000 // DPLL2 control register.
#define CLKM_DPLL3CTL 0xfffed100 // DPLL3 control register.
//Bit Definitions
#define ARM_IDLE BIT11 // MCU Idle Bit
#define WKUP_MODE BIT10 // WKUP Mode
#define IDLTIM_ARM BIT9 // Idle Timers
#define IDLAPI_ARM BIT8 // Idle API
#define IDLDPLL_ARM BIT7 // Idle DPLL
#define IDLIF_ARM BIT6 // Idle DMA, TC, Rhea
#define IDLHSAB_ARM BIT5 // Idle High Speed Bus
#define IDLLB_ARM BIT4 // Idle Local Bus
#define EN_LBFREECK BIT10 // Local Bus Free Clock
#define EN_GPIOCK BIT9 // GPIO Clock
#define DMACK_REG BIT8 // Permanent DMA Clock
#define EN_TIMCK BIT7 // Timers Clock
#define EN_API_CK BIT6 // API Clock
#define EN_HSABCK BIT5 // High speed Bus Clock
#define EN_LBCK BIT4 // Enable Local Bus Clock
#define IDLTIM_DSP BIT8 // Timer Idle
#define IDLGPIO_DSP BIT7 // GPIO Idle
#define IDLUART_DSP BIT3 // UART Idle
#define IDLPER_DSP BIT2 // External Peripheral Clock Idle
#define IDLXORP_DSP BIT1 // External VTCXO Peripheral Clock Idle
#define IDLWDT_DSP BIT0 // Watchdog Clock Idle
#define EN_DSPTIMCK BIT5 // Timer Clock Enable
#define EN_DSPGPIOCK BIT4 // GPIO Clock Enable
#define EN_UARTCK BIT3 // UART Clock Enable
#define IDLLCD_ARM BIT3 // LCD Clock Idle
#define IDLXORP_ARM BIT2 // External Peripheral Clock Idle
#define IDLPER_ARM BIT1 // External VTCXO Peripheral Clock Idle
#define IDLWDT_ARM BIT0 // Watchdog Clock Idle
#define EN_LCDCK BIT3 // LCD Clock Enable
#define EN_PERCK BIT2 // External Peripheral Clock Enable
#define EN_XORPCK BIT1 // External VTCXO Peripheral Clock Enable
#define EN_WDTCK BIT0 // Watchdog Clock Enable
#define BYPASS_1D 0x2000 // Bypass mode, 1/1 = 13.0 / 12.0 MHz.
#define DPLLEN_1X 0x2090 // DPLL mode, 1/1 = 13.0 / 12.0 MHz.
#define CLKM_MCU_SYSST_CONFIG 0x00000380 // Mask for configuration status bits.
///////////////////////////////////////////////////////////////////////////////
// Rhea bridge.
///////////////////////////////////////////////////////////////////////////////
#define RHEA1_BASE 0xfffeca00 // Internal.
#define RHEA2_BASE 0xfffed300 // External.
#define RHEA_CONTROL 0x00
#define RHEA_BUS_ALLOC 0x04
#define RHEA_ARM_CONTROL 0x08
#define RHEA_ENH_CONTROL 0x0c
///////////////////////////////////////////////////////////////////////////////
// Hi-Res (32 bit) Timers.
///////////////////////////////////////////////////////////////////////////////
#define TIMER1_BASE 0xfffec500
#define TIMER2_BASE 0xfffec600
#define TIMER3_BASE 0xfffec700
#define TIMER1_CNTL_TIMER (TIMER1_BASE+0x00)
#define TIMER1_LOAD_TIM (TIMER1_BASE+0x04)
#define TIMER1_READ_TIM (TIMER1_BASE+0x08)
#define TIMER_CNTL_OFFS 0x00
#define TIMER_LOAD_OFFS 0x04
#define TIMER_READ_OFFS 0x08
// Timer 2 constants (not used if RTDX is emulation based)
#define TIMER2_CNTL_TIMER (TIMER2_BASE+0x00)
#define TIMER2_LOAD_TIM (TIMER2_BASE+0x04)
#define TIMER2_READ_TIM (TIMER2_BASE+0x08)
#define TIMER2_CNTL_TIMER_ST BIT0
#define TIMER2_CNTL_TIMER_AR BIT1
#define TIMER2_CNTL_TIMER_PTV_0 BIT2
#define TIMER2_CNTL_TIMER_PTV_1 BIT3
#define TIMER2_CNTL_TIMER_PTV_2 BIT4
#define TIMER2_CNTL_TIMER_CK_EN BIT5
#define TIMER2_CNTL_TIMER_FREE BIT6
#define TIMER2_CNTL_TIMER_SOFT BIT7
///////////////////////////////////////////////////////////////////////////////
// 32KHz Timers.
///////////////////////////////////////////////////////////////////////////////
#define TIM32K_BASE 0xfffb9000
#define TIM32K_LOAD_OFFSET 0x00
#define TIM32K_COUNT_OFFSET 0x04
#define TIM32K_CONTROL_OFFSET 0x08
#define TIM32K_LOAD_ADDR (TIM32K_BASE+TIM32K_LOAD_OFFSET)
#define TIM32K_COUNT_ADDR (TIM32K_BASE+TIM32K_COUNT_OFFSET)
#define TIM32K_CONTROL_ADDR (TIM32K_BASE+TIM32K_CONTROL_OFFSET)
///////////////////////////////////////////////////////////////////////////////
// DSP MMU.
///////////////////////////////////////////////////////////////////////////////
#define DSP_MMU_BASE 0xfffed200
#define DSP_MMU_CONTROL (DSP_MMU_BASE+0x08) // Control Register.
///////////////////////////////////////////////////////////////////////////////
// Local bus MMU.
///////////////////////////////////////////////////////////////////////////////
#define LB_MMU_BASE 0xfffec200
#define LB_MMU_CONTROL (LB_MMU_BASE+0x08) // Control Register.
///////////////////////////////////////////////////////////////////////////////
// Local bus interface.
///////////////////////////////////////////////////////////////////////////////
#define LBI_BASE 0xfffec100
#define LBI_CLOCK_DIVISOR (LBI_BASE+0x0c)
///////////////////////////////////////////////////////////////////////////////
// Interrupt controller.
///////////////////////////////////////////////////////////////////////////////
#define INTC_BASE 0xfffecb00
#define INTC_L2_BASE 0xfffe0000
#define INTC_IIR 0x00 // Bitmask OR of all active edge-sensitive interrupts.
#define INTC_MIR 0x04 // Mask Interrupt register.
#define INTC_IRQ 0x08 // Interrupt Source : bitmask of single active IRQ.
#define INTC_FIQ 0x0c // Interrupt Source : bitmask of single active FIQ.
#define INTC_IRQB 0x10 // Interrupt Source : index of active IRQ.
#define INTC_FIQB 0x14 // Interrupt Source : index of active FIQ.
#define INTC_ACK 0x18 // Interrupt Acknowledge.
#define INTC_ILR_IRQ0 0x1c // Interrupt Level register 0 (others follow).
#define INTC_ISR 0x9c // Interrupt set register.
// Mask all interrupts.
#define INTC_MIR_MASK_ALL_INTR 0xffffffff
// ILR register default settings.
#define INTC_ILR_FIQ (BIT0) // 0=IRQ, 1=FIQ.
#define INTC_ILR_SENSE (BIT1) // 0=Edge, 1=Level.
#define INTC_ILR_PRTY (BIT6|BIT5|BIT4|BIT3|BIT2)
#define INTC_ILR_LEVEL INTC_ILR_SENSE // IRQ, Level, Priority 0 (Highest).
#define INTC_ILR_EDGE 0 // IRQ, Edge, Priority 0 (Highest).
// Definition of ACK register.
#define INTC_ACK_IRQ BIT0 // Set to one to acknowledge IRQ.
#define INTC_ACK_FIQ BIT1 // Set to one to acknowledge FIQ.
#define INTC_IRQ_FIQ_CASCADE 0x00
#define INTC_IRQ_IRQ_CASCADE 0x01
#define INTC_IRQ_USB 0x02
#define INTC_IRQ_USB_SOF 0x03
#define INTC_IRQ_MCBSP2_TX 0x04 // Referred to as Modem Data I/F (sometimes SPI) McBSP.
#define INTC_IRQ_MCBSP2_RX 0x05
#define INTC_IRQ_CAMERA 0x06
#define INTC_IRQ_EXT0 0x07
#define INTC_IRQ_EXT1 0x08
#define INTC_IRQ_ABORT 0x09
#define INTC_IRQ_DSP_MAIL1 0x0a
#define INTC_IRQ_DSP_MAIL2 0x0b
#define INTC_IRQ_HSB_MAIL 0x0c
#define INTC_IRQ_RHEA_PRV 0x0d
#define INTC_IRQ_GPIO 0x0e
#define INTC_IRQ_UART0 0x0f
#define INTC_IRQ_TIMER3 0x10
#define INTC_IRQ_LB_MMU 0x11
#define INTC_IRQ_HSB_MMU 0x12
#define INTC_IRQ_DMA_CH0_CH6 0x13
#define INTC_IRQ_DMA_CH1_CH7 0x14
#define INTC_IRQ_DMA_CH2_CH8 0x15
#define INTC_IRQ_DMA_CH3 0x16
#define INTC_IRQ_DMA_CH4 0x17
#define INTC_IRQ_DMA_CH5 0x18
#define INTC_IRQ_DMA_LCD 0x19
#define INTC_IRQ_TIMER1 0x1a
#define INTC_IRQ_WDTIMER 0x1b
#define INTC_IRQ_RHEA_PUB 0x1c
#define INTC_IRQ_LOCALBUS 0x1d
#define INTC_IRQ_TIMER2 0x1e
#define INTC_IRQ_LCD 0x1f
// Interrupt controller cascade (for actual HW controller ID, subtract 0x20).
#define INTC_IRQ_HW_ERR 0x20
#define INTC_IRQ_KEYBOARD 0x21
#define INTC_IRQ_UWIRE_TX 0x22
#define INTC_IRQ_UWIRE_RX 0x23
#define INTC_IRQ_I2C 0x24
#define INTC_IRQ_MPUIO 0x25
#define INTC_IRQ_EXT2 0x26
#define INTC_IRQ_EXT3 0x27
#define INTC_IRQ_EXT4 0x28
#define INTC_IRQ_EXT5 0x29
#define INTC_IRQ_MCBSP1_TX 0x2a // Referred to as Optical McBSP.
#define INTC_IRQ_MCBSP1_RX 0x2b
#define INTC_IRQ_MCBSP0_TX 0x2c // Referred to as Audio McBSP.
#define INTC_IRQ_MCBSP0_RX 0x2d
#define INTC_IRQ_UART1 0x2e // Referred to as Blue Tooth I/F UART.
#define INTC_IRQ_UART2 0x2f // Referred to as Com I/F UART.
#define INTC_IRQ_MCSI0_TX 0x30 // Referred to as Blue Tooth Voice I/F MCSI.
#define INTC_IRQ_MCSI0_RX 0x31
#define INTC_IRQ_MCSI0_FRM_ERR 0x32
#define INTC_IRQ_MCSI1_TX 0x33 // Referred to as Modem Voice I/F (sometimes SPI) MCSI.
#define INTC_IRQ_MCSI1_RX 0x34
#define INTC_IRQ_MCSI1_FRM_ERR 0x35
#define INTC_IRQ_T32K 0x36
#define INTC_IRQ_MMC 0x37
#define INTC_IRQ_ULPD 0x38
#define INTC_IRQ_RTC_PER 0x39
#define INTC_IRQ_RTC_ALARM 0x3a
#define INTC_IRQ_RSVD0 0x3b
#define INTC_IRQ_DSP_MMU 0x3c
#define INTC_IRQ_USB_GEN 0x3d
#define INTC_IRQ_USB_SBI 0x3e
#define INTC_IRQ_MCBSP2_RX_OVR 0x3f
///////////////////////////////////////////////////////////////////////////////
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