?? omap.h
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// Watchdog timer.
///////////////////////////////////////////////////////////////////////////////
#define WDTIM_BASE 0xfffec800
#define WDTIM_CONTROL (WDTIM_BASE+0x00)
#define WDTIM_LOAD (WDTIM_BASE+0x04)
#define WDTIM_READ (WDTIM_BASE+0x04)
#define WDTIM_MODE (WDTIM_BASE+0x08)
// Values to write to mode register to disable the watchdog function.
#define DISABLE_SEQ1 0xF5
#define DISABLE_SEQ2 0xA0
// WDTIM_CONTROL bit definitions.
#define WDTIM_CONTROL_ST BIT7
///////////////////////////////////////////////////////////////////////////////
// UARTs.
///////////////////////////////////////////////////////////////////////////////
#define UART0_BASE 0xfffce800 // Referred to as Gigacell UART.
#define UART1_BASE 0xfffb0000 // Referred to as Blue Tooth I/F UART, UART_MODEM.
#define UART2_BASE 0xfffb0800 // Referred to as Com I/F UART, UART_IRDA.
// Register offsets.
#define UART_RHR 0x00 // RCXV holding register
#define UART_THR 0x00 // TX holding register
#define UART_DLL 0x00 // UART divisor latch clock lsb
#define UART_IER 0x01 // UART mode interrupt enable
#define UART_DLH 0x01 // UART divisor latch clock msb
#define UART_IIR 0x02 // Interupt identifiation register
#define UART_FCR 0x02 // FIFO control register
#define UART_EFR 0x02 // Enhanced Feature Register
#define IRDA_IIR 0x02 // SIR inter identification register
#define UART_LCR 0x03 // Line Control Register
#define UART_MCR 0x04 // MODEM Control Register
#define UART_XON1 0x04 // UART XON1 character
#define UART_WORD1 0x04 // IRDA address1 character
#define UART_LSR 0x05 // Line Status Register
#define UART_XON2 0x05 // UART XON2 character
#define UART_WORD2 0x05 // IRDA address2 character
#define UART_MSR 0x06 // Modem Status
#define UART_TCR 0x06 // Transmission Control Register
#define UART_XOFF1 0x06 // UART XOFF1 character
#define UART_XOFF2 0x07 // UART XOFF2 character
#define UART_SPR 0x07 // UART scratchpad register
#define UART_TLR 0x07 // Trigger Level Register
#define UART_MDR1 0x08 // Model Definition Register 1
#define UART_MDR2 0x09 // Model Definition Register 2
#define IRDA_TXFLL 0x0A // Transmit Frame Length lsb
#define IRDA_SFLSR 0x0A // STATUS FIFO Line Status Register
#define IRDA_TXFLH 0x0B // Transmit Frame Length msb
#define IRDA_RESUME 0x0B // Resume register (dummy)
#define IRDA_RXFLL 0x0C // Receive Frame Length lsb
#define IRDA_SFREGL 0x0C // Status FIFO register lsb
#define IRDA_SFREGH 0x0D // Status FIFO register lsb
#define IRDA_RXFLH 0x0D // Receive Frame Length msb
#define IRDA_BLR 0x0E // BOF Length Register
#define IRDA_ACREG 0x0F // Auxilliary Control Register
#define IRDA_DIV16 0x0F // DIV 1.6
#define UART_SCR 0x10 // Supplememtary Control Register
#define UART_SSR 0x11 // Supplememtary Status Register
#define UART_EBLR 0x12 // Extended BOF Length Register
#define OSC_12M 0x13 // Oscillator 12 MHz.
// IER register bit masks
#define IER_RHR_IT BIT0 // IER RHR enable
#define IER_THR_IT BIT1 // IER THR enable
#define IER_LINE_STS_IT BIT2 // IER line status enable
#define IER_MODEM_STS_IT BIT3 // IER modem status enable
#define IER_SLEEP_MODE BIT4 // IER sleep mode enable
#define IER_XOFF_IT BIT5 // IER xoff enable
#define IER_RTS_IT BIT6 // IER rts enable
#define IER_CTS_IT BIT7 // IER cts enable
// IIR register bit masks
#define IIR_IT_PENDING BIT0 // IIR interrupt pending
#define IIR_IT_TYPE 0x3E // IIR interrupt type
// Pri Src 5 4 3 2 1 0
// 1 0 0 0 1 1 0 RX line status
// 2 0 0 0 1 0 0 RX Timeout
// 2 0 0 1 1 0 0 RHR Intr
// 3 0 0 0 0 1 0 THR Intr
// 4 0 0 0 0 0 0 Modem Intr
// 5 0 1 0 0 0 0 XOFF/Special char
// 6 1 0 0 0 0 0 CTS RTS change
// FCR register bit masks
#define FCR_FIFO_EN BIT0 // FIFO enable mask bit
#define FCR_RX_FIFO_CLEAR BIT1 // FIFO rx clear
#define FCR_TX_FIFO_CLEAR BIT2 // FIFO tx clear
#define FCR_DMA_MODE BIT3 // FIFO DMA mode
#define FCR_TX_FIFO_TRIG (BIT4|BIT5) // FIFO TX FIFO trigger level
#define FCR_RX_FIFO_TRIG (BIT6|BIT7) // FIFO RX FIFO trigger level
// EFR register bit masks
#define EFR_SW_FLOW_CONTROL 0x0F // EFR sw flow control
#define EFR_ENHANCED_EN BIT4 // EFR enhanced functions write enable
#define EFR_SPECIAL_CHAR_DETECT BIT5 // EFR special char detect
#define EFR_AUTO_RTS_EN BIT6 // EFR auto rts enable
#define EFR_AUTO_CTS_EN BIT7 // EFR auto cts enable
// LCR register bit masks
#define LCR_CHAR_LENGTH (BIT0|BIT1) // LCR character length
#define LCR_NB_STOP BIT2 // LCR number of stop bits
#define LCR_PARITY_EN BIT3 // LCR parity enable
#define LCR_PARITY_TYPE1 BIT4 // LCR parity type1
#define LCR_PARITY_TYPE2 BIT5 // LCR parity type2
#define LCR_BREAK_EN BIT6 // LCR break enable
#define LCR_DIV_EN BIT7 // LCR divisor latch enable
// MCR register bit masks
#define MCR_DCD BIT0 // MCR DCD
#define MCR_RTS BIT1 // MCR RTS
#define MCR_LOOPBACK BIT4 // MCR loopback enable
#define MCR_XON BIT5 // MCR xon enable
#define MCR_TCR_TLR BIT6 // MCR access to tcr tlr registers
#define MCR_CLKSEL BIT7 // MCR divide clock input/4
// MSR register bit masks
#define MSR_CTS_STS BIT0 // MSR cts input changed state (loopback)
#define MSR_DSR_STS BIT1 // MSR mcr input changed state (loopback)
#define MSR_NCTS_STS BIT4 // MSR complement of CTS input
#define MSR_NDSR_STS BIT5 // MSR equiv to MCR (loopback)
// LSR register bit masks
#define LSR_RX_FIFO BIT0 // LSR rx fifo status
#define LSR_RX_OE BIT1 // LSR overrun error
#define LSR_RX_PE BIT2 // LSR parity error
#define LSR_RX_FE BIT3 // LSR framing error
#define LSR_RX_BI BIT4 // LSR break indicator
#define LSR_TX_FIFO BIT5 // LSR tx fifo status
#define LSR_TX_SR BIT6 // LSR tx fifo and sr status
#define LSR_FIFO_STS BIT7 // LSR errors in fifo
// SIR LSR register bit masks
#define IRDA_RX_FIFO BIT0 // LSR rx fifo status
#define IRDA_STS_FIFO BIT1 // LSR status fifo
#define IRDA_CRC BIT2 // LSR crc error
#define IRDA_ABORT BIT3 // LSR abort pattern
#define IRDA_FRAME_TOO_LONG BIT4 // LSR frame too long
#define IRDA_RX_LAST_BYTE BIT5 // LSR rx last byte
#define IRDA_STS_FIFO_FULL BIT6 // LSR sts fifo full
#define IRDA_THR_EMPTY BIT7 // LSR tx hold register empty
// SIR IER register bit masks
#define IRDA_RHR_IT BIT0 // IER RHR enable intr
#define IRDA_THR_IT BIT1 // IER THR enable intr
#define IRDA_LAST_RX_BYTE_IT BIT2 // IER Last byte in frame intr
#define IRDA_RX_OVERRUN_IT BIT3 // IER rx overrun enable intr
#define IRDA_STS_FIFO_TRIG_IT BIT4 // IER status FIFO enable intr
#define IRDA_TX_UNDERRUN_IT BIT5 // IER tx underrun enable intr
#define IRDA_LINE_STS_IT BIT6 // IER receive line status intr
#define IRDA_EOF_IT BIT7 // IER eof enable intr
// SIR IIR register bit masks
#define IRDA_RX_FIFO_LAST_BYTE_IT BIT2 // IER Last byte in frame intr
#define IRDA_RX_OE_IT BIT3 // IER rx overrun intr
#define IRDA_FIFO_IT BIT4 // IER status FIFO intr
#define IRDA_TX_UE_IT BIT5 // IER tx underrun intr
// SCR register bit masks
#define SCR_DMA_MODE_CTL BIT0 // SCR dma mode control
#define SCR_DMA_MODE_2 0x06 // SCR dma mode
#define SCR_TX_EMPTY_CTL BIT3 // SCR empty intr
#define SCR_RX_CTS_WAKE BIT4 // SCR wake up intr
#define SCR_TX_TRIG_GRANU1 BIT6 // SCR TX Trigger Granularity of 1
#define SCR_RX_TRIG_GRANU1 BIT7 // SCR RX Trigger Granularity of 1
// SSR register bit masks
#define SSR_FIFO_FULL BIT0 // SSR fifo full status
#define SSR_RX_CTS_WAKE_STS BIT1 // SSR falling edge detect on RX or CTS
// XON1 register bit masks
#define XON1_XON_WORD1 0xFF // UART XON1 character
// XOFF1 register bit masks
#define XOFF1_XOFF_WORD1 0xFF // UART XOFF1 character
// XON2 register bit masks
#define XON2_XON_WORD2 0xFF // UART XON2 character
// XOFF2 register bit masks
#define XOFF2_XOFF_WORD2 0xFF // UART XOFF2 character
// SPR register bit masks
#define SPR_SPR_WORD 0xFF // UART scratchpad register
// DLL register bit masks
#define DLL_CLOCK_LSB 0xFF // UART 8-bit lsb divisor
// DLH register bit masks
#define DLH_CLOCK_MSB 0xFF // UART 8-bit msb divisor
// TCR register bit masks
#define TCR_RX_FIFO_TRIG_HALT 0x0F // RCV FIFO trigger halt xmit
#define TCR_RX_FIFO_TRIG_START 0xF0 // RCV FIFO trigger level to restore (0-60)
// TLR register bit masks
#define TLR_TX_FIFO_TRIG_DMA 0x0F // TXmit FIFO trigger level (4-60)
#define TLR_RX_FIFO_TRIG_DMA 0xF0 // RCv FIFO trigger level (4-60)
// MDR1 register bit masks
#define MDR1_MODE_SELECT 0x03 // Mode select
// 000 - uart mode
// 001 - sir mode
// 010 - uart autobauding
// 111 - reset state
#define MDR1_IR_SLEEP BIT3 // sleep mode enable
#define MDR1_SCT BIT5 // store and control xmit
#define MDR1_FRAME_END_MODE BIT7 // frame length method
// MDR2 register bit masks
#define MDR2_STS_FIFO_TRIG 0x06 // FIFO threshold select
// 00 - 1 chars
// 01 - 4 chars
// 10 - 7 chars
// 11 - 8 chars
#define MDR2_DIV_16M 0x18 // MSB part of DIV_16
// SFLSR register bit masks
#define SFLSR_CRC_ERROR BIT1 // error in frame at top of fifo
#define SFLSR_ABORT_DETECT BIT2 // abort in frame at top of fifo
#define SFLSR_FRAME_LENGTH_ERROR BIT3 // frame length error at top of fifo
#define SFLSR_OE_ERROR BIT4 // overrun error at top of rx fifo
// RESUME register bit masks
#define RESUME_DI 0xFF // Used to restart TX or RX after fault
// BOF register bit masks
#define BOF_NB_START 0x3F // num of start flags (xbof BOF) for xmit (0-63)
#define BOF_XBOF_TYPE BIT6 // SIR BOF Select
// 0 = 0xff
// 1 = 0xC0
#define BOF_STS_FIFO_RESET BIT7 // Status FIFO reset
// DIV16 register bit masks
#define DIV16_DIV16L 0xFF // used to generate DIV 1.6 us pulse
// ACREG register bit masks
#define ACREG_EOT_EN BIT0 // end of transmission bits
#define ACREG_ABORT_EN BIT1 // frame abort
#define ACREG_SCTX_EN BIT2 // start frame tx
#define ACREG_DIS_IR_RX BIT5 // Disable RXIR input
#define ACREG_SD_MOD BIT6 // SD_MODE control
#define ACREG_PULSE_TYPE BIT7 // SIR pulse width 3/16 or 1.6us
// EFR
#define ENHANCED_FEATURE_BIT BIT4
///////////////////////////////////////////////////////////////////////////////
// ICR.
///////////////////////////////////////////////////////////////////////////////
#define ICR_BASE 0xfffbb800 // Interprocessor Communication register.
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