#define M_ICR_REG_ADDR              (ICR_BASE+M_ICR_REG_OFFSET)
#define G_ICR_REG_ADDR              (ICR_BASE+G_ICR_REG_OFFSET)
#define M_CTL_REG_ADDR              (ICR_BASE+M_CTL_REG_OFFSET)
#define G_CTL_REG_ADDR              (ICR_BASE+G_CTL_REG_OFFSET)
#define PM_BA_REG_ADDR              (ICR_BASE+PM_BA_REG_OFFSET)
#define DM_BA_REG_ADDR              (ICR_BASE+DM_BA_REG_OFFSET)
#define RM_BA_REG_ADDR              (ICR_BASE+RM_BA_REG_OFFSET)
#define DPRAM_ADDR                  (ICR_BASE+DPRAM_OFFSET)
///////////////////////////////////////////////////////////////////////////////
// TCIF
///////////////////////////////////////////////////////////////////////////////
#define TCIF_BASE                   0xfffea800 
#define TCIF_TCIF_CTL               (TCIF_BASE+0x00)
#define TCIF_PGM_CACHE_CTL          (TCIF_BASE+0x02)
#define TCIF_DATA_CACHE_CTL         (TCIF_BASE+0x04)
#define TCIF_RAND_BUFFER_CTL        (TCIF_BASE+0x06)
#define TCIF_IT_DESCRIPTION         (TCIF_BASE+0x10)
#define TCIF_IT_ADDRESS_L           (TCIF_BASE+0x12)
#define TCIF_IT_ADDRESS_H           (TCIF_BASE+0x14)
///////////////////////////////////////////////////////////////////////////////
// Perseus configuration.
///////////////////////////////////////////////////////////////////////////////
#define P_CONF_BASE                 0xfffe1000              // Perseus configuration.
#define PERSEUS_DIE_ID0_OFFSET      0x10 
#define PERSEUS_DIE_ID1_OFFSET      0x12 
#define PERSEUS_DIE_ID2_OFFSET      0x14
#define PERSEUS_DIE_ID3_OFFSET      0x16
#define PERSEUS_DEBUG_OFFSET        0x18
#define PERSEUS_MODE2_OFFSET        0x1A
#define PERSEUS_MODE1_OFFSET        0x1C
#define PERSEUS_CONF0_OFFSET        0x1E
#define PERSEUS_CONF1_OFFSET        0x20
#define PERSEUS_CONF2_OFFSET        0x22
#define PERSEUS_CONF3_OFFSET        0x24
#define PERSEUS_CONF4_OFFSET        0x26
#define PERSEUS_CONF5_OFFSET        0x28
#define PERSEUS_CONF6_OFFSET        0x2A
#define PERSEUS_CONF7_OFFSET        0x2C
#define PERSEUS_CONF8_OFFSET        0x2E
#define PERSEUS_CONF9_OFFSET        0x30
#define PERSEUS_AUDIO_CONF_OFFSET   0x32
#define PERSEUS_DIE_ID0             (P_CONF_BASE+PERSEUS_DIE_ID0_OFFSET) 
#define PERSEUS_DIE_ID1             (P_CONF_BASE+PERSEUS_DIE_ID1_OFFSET)
#define PERSEUS_DIE_ID2             (P_CONF_BASE+PERSEUS_DIE_ID2_OFFSET)
#define PERSEUS_DIE_ID3             (P_CONF_BASE+PERSEUS_DIE_ID3_OFFSET)
#define PERSEUS_MODE2               (P_CONF_BASE+PERSEUS_MODE2_OFFSET)
#define PERSEUS_MODE1               (P_CONF_BASE+PERSEUS_MODE1_OFFSET)
#define PERSEUS_CONF0               (P_CONF_BASE+PERSEUS_CONF0_OFFSET)
#define PERSEUS_CONF1               (P_CONF_BASE+PERSEUS_CONF1_OFFSET)
#define PERSEUS_CONF2               (P_CONF_BASE+PERSEUS_CONF2_OFFSET)
#define PERSEUS_CONF3               (P_CONF_BASE+PERSEUS_CONF3_OFFSET)
#define PERSEUS_CONF4               (P_CONF_BASE+PERSEUS_CONF4_OFFSET)
#define PERSEUS_CONF5               (P_CONF_BASE+PERSEUS_CONF5_OFFSET)
#define PERSEUS_CONF6               (P_CONF_BASE+PERSEUS_CONF6_OFFSET)
#define PERSEUS_CONF7               (P_CONF_BASE+PERSEUS_CONF7_OFFSET)
#define PERSEUS_CONF8               (P_CONF_BASE+PERSEUS_CONF8_OFFSET)
#define PERSEUS_CONF9               (P_CONF_BASE+PERSEUS_CONF9_OFFSET)
#define PERSEUS_AUDIO_CONF          (P_CONF_BASE+PERSEUS_AUDIO_CONF_OFFSET)

#define PERSEUS_DEBUG_MODE          (BIT2|BIT3|BIT4|BIT5)   // Mask for func/debug mode bits.
///////////////////////////////////////////////////////////////////////////////
// Helen configuration.
///////////////////////////////////////////////////////////////////////////////
#define HELEN_CONF_BASE             0xfffe1000
#define HELEN_FUNC_MUX_CTRL0_OFFSET 0x00
#define HELEN_FUNC_MUX_CTRL1_OFFSET 0x04
#define HELEN_FUNC_MUX_CTRL2_OFFSET 0x08
#define HELEN_FUNC_MUX_CTRL0        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL0_OFFSET)
#define HELEN_FUNC_MUX_CTRL1        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL1_OFFSET)
#define HELEN_FUNC_MUX_CTRL2        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL2_OFFSET)
#define HELEN_DEVICE_ID_REGISTER    0xfffed404 // This address on the HelenDC corresponds to 
                                               // the JTAG ID code, however reading this 
                                               // on the HelenDC does not return the 
                                               // proper value as it does via JTAG (0xB31F), 
                                               // However on Helen1 it gives 0x1b47002f
#define HELEN_TEST_DBG_CTRL0_OFFSET  0x70
#define HELEN_TEST_DBG_CTRL0       (HELEN_CONF_BASE+HELEN_TEST_DBG_CTRL0_OFFSET)
#define HELEN_DEVICE_ID_REGISTER    0xfffed404
#define HELEN_CONF_BASE              0xfffe1000
#define HELEN_FUNC_MUX_CTRL0_OFFSET  0x00
#define HELEN_FUNC_MUX_CTRL1_OFFSET  0x04
#define HELEN_FUNC_MUX_CTRL2_OFFSET  0x08
#define HELEN_COMP_MODE_CTRL0_OFFSET 0x0C
#define HELEN_FUNC_MUX_CTRL3_OFFSET  0x10
#define HELEN_FUNC_MUX_CTRL4_OFFSET  0x14
#define HELEN_FUNC_MUX_CTRL5_OFFSET  0x18
#define HELEN_FUNC_MUX_CTRL6_OFFSET  0x1C
#define HELEN_FUNC_MUX_CTRL7_OFFSET  0x20
#define HELEN_FUNC_MUX_CTRL8_OFFSET  0x24
#define HELEN_FUNC_MUX_CTRL9_OFFSET  0x28
#define HELEN_FUNC_MUX_CTRLA_OFFSET  0x2C
#define HELEN_FUNC_MUX_CTRLB_OFFSET  0x30
#define HELEN_FUNC_MUX_CTRLC_OFFSET  0x34
#define HELEN_FUNC_MUX_CTRLD_OFFSET  0x38
#define HELEN_PULL_DWN_DTRL0_OFFSET  0x40
#define HELEN_PULL_DWN_DTRL1_OFFSET  0x44
#define HELEN_PULL_DWN_DTRL2_OFFSET  0x48
#define HELEN_PULL_DWN_DTRL3_OFFSET  0x4C
#define HELEN_GATE_INH_CTRL0_OFFSET  0x50
#define HELEN_VOLTAGE_CTRL0_OFFSET   0x60
#define HELEN_TEST_DBG_CTRL0_OFFSET  0x70
#define HELEN_MOD_CONF_CTRL0_OFFSET  0x80
#define HELEN_FUNC_MUX_CTRL0        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL0_OFFSET)
#define HELEN_FUNC_MUX_CTRL1        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL1_OFFSET)
#define HELEN_FUNC_MUX_CTRL2        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL2_OFFSET)
#define HELEN_COMP_MODE_CTRL0       (HELEN_CONF_BASE+HELEN_COMP_MODE_CTRL0_OFFSET)
#define HELEN_FUNC_MUX_CTRL3        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL3_OFFSET)
#define HELEN_FUNC_MUX_CTRL4        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL4_OFFSET)
#define HELEN_FUNC_MUX_CTRL5        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL5_OFFSET)
#define HELEN_FUNC_MUX_CTRL6        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL6_OFFSET)
#define HELEN_FUNC_MUX_CTRL7        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL7_OFFSET)
#define HELEN_FUNC_MUX_CTRL8        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL8_OFFSET)
#define HELEN_FUNC_MUX_CTRL9        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRL9_OFFSET)
#define HELEN_FUNC_MUX_CTRLA        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRLA_OFFSET)
#define HELEN_FUNC_MUX_CTRLB        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRLB_OFFSET)
#define HELEN_FUNC_MUX_CTRLC        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRLC_OFFSET)
#define HELEN_FUNC_MUX_CTRLD        (HELEN_CONF_BASE+HELEN_FUNC_MUX_CTRLD_OFFSET)
#define HELEN_PULL_DWN_DTRL0        (HELEN_CONF_BASE+HELEN_PULL_DWN_DTRL0_OFFSET)
#define HELEN_PULL_DWN_DTRL1        (HELEN_CONF_BASE+HELEN_PULL_DWN_DTRL1_OFFSET)
#define HELEN_PULL_DWN_DTRL2        (HELEN_CONF_BASE+HELEN_PULL_DWN_DTRL2_OFFSET)
#define HELEN_PULL_DWN_DTRL3        (HELEN_CONF_BASE+HELEN_PULL_DWN_DTRL3_OFFSET)
#define HELEN_GATE_INH_CTRL0        (HELEN_CONF_BASE+HELEN_GATE_INH_CTRL0_OFFSET)
#define HELEN_VOLTAGE_CTRL0         (HELEN_CONF_BASE+HELEN_VOLTAGE_CTRL0_OFFSET) 
#define HELEN_TEST_DBG_CTRL0        (HELEN_CONF_BASE+HELEN_TEST_DBG_CTRL0_OFFSET)
#define HELEN_MOD_CONF_CTRL0        (HELEN_CONF_BASE+HELEN_MOD_CONF_CTRL0_OFFSET)
///////////////////////////////////////////////////////////////////////////////
// LCD controller.
///////////////////////////////////////////////////////////////////////////////
#define LCD_BASE                    0xfffec000
//
// Offset of LCDCONTROL register and its register definition.
//
#define LCD_LCDCONTROL_OFFSET       0x00000000  // Control register offset address
#define LCD_LCDCONTROL_MASK         0x000FF38B  // Read Register & this = valid value
#define LCD_LCDCONTROL_RESET        0x00000000  // Reset value of register
#define LCD_LCDCONTROL_RSVD1        0xFFF00000  // Reserved bank of bits
#define LCD_LCDCONTROL_FDD          0x000FF000  // FIFO DMA Request Delay, in memory clock cycles
#define LCD_LCDCONTROL_RSVD2        (BIT10|BIT11)  // Reserved bank of bits
#define LCD_LCDCONTROL_M8B          BIT9        // Monochrome mode bit
#define LCD_LCDCONTROL_LCDBE        BIT8        // LCD Big Endian Enable
#define LCD_LCDCONTROL_LCDTFT       BIT7        // LCD TFT/DSTN select
#define LCD_LCDCONTROL_RSVD3        (BIT3|BIT4|BIT5)  // Reserved bank of bits
#define LCD_LCDCONTROL_DONEMASK     BIT2        // LCD Vsync Interrupt Mask
#define LCD_LCDCONTROL_LCDBW        BIT1        // Monochrome/Color Select
#define LCD_LCDCONTROL_LCDEN        BIT0        // LCD Controller Enable
//
// Offset of LCDSTATUS register and its register definition.
//
#define LCD_LCDSTATUS_OFFSET        0x00000010  // Status register offset address
#define LCD_LCDSTATUS_MASK          0x0000002D  // Read Register & this = valid value
#define LCD_LCDSTATUS_RESET         0x00000000  // Reset value of register
#define LCD_LCDSTATUS_RSVD1         0xFFFFFFC0  // Reserved bank of bits
#define LCD_LCDSTATUS_FUF           BIT5        // FIFO Underflow Status
#define LCD_LCDSTATUS_RSVD2         BIT4        // Reserved bank of bits
#define LCD_LCDSTATUS_ABC           BIT3        // AC Bias Count Status
#define LCD_LCDSTATUS_SYNC          BIT2        // Sync Loss Status
#define LCD_LCDSTATUS_RSVD3         BIT1        // Reserved bank of bits
#define LCD_LCDSTATUS_DONE          BIT0        // LCD Frame Done Status
//
// Offset of LCDTIMING0 register and its register definition.
//
#define LCD_LCDTIMING0_OFFSET       0x00000004  // Timing 0 register offset address
#define LCD_LCDTIMING0_RESET        0x00000000  // Reset value of register -- UNKNOWN???
#define LCD_LCDTIMING0_HBP          0xFF000000  // Horizontal Back Porch, in pixel clocks - 1
#define LCD_LCDTIMING0_HFP          0x00FF0000  // Horizontal Front Porch, in pixels clocks - 1
#define LCD_LCDTIMING0_HSW          0x0000FC00  // Horizontal Sync Pulse Width, in pixel clocks - 1
#define LCD_LCDTIMING0_PPL          0x000003FF  // Pixels per line, in pixels - 1
//
// Offset of LCDTIMING1 register and its register definition.
//
#define LCD_LCDTIMING1_OFFSET       0x00000008  // Timing 1 register offset address
#define LCD_LCDTIMING1_RESET        0x00000000  // Reset value of register
#define LCD_LCDTIMING1_VBP          0xFF000000  // Vertical Back Porch, in lines
#define LCD_LCDTIMING1_VFP          0x00FF0000  // Vertical Front Porch, in lines
#define LCD_LCDTIMING1_VSW          0x0000FC00  // Vertical Sync Pulse Width, in lines - 1
#define LCD_LCDTIMING1_LPP          0x000003FF  // Lines per panel, in lines - 1
//
// Offset of LCDTIMING2 register and its register definition.
//
#define LCD_LCDTIMING2_OFFSET       0x0000000C  // Timing 2 register offset address
#define LCD_LCDTIMING2_RESET        0x00000000  // Reset value of register
#define LCD_LCDTIMING2_RSVD1        0xFF000000  // Reserved bits of register
#define LCD_LCDTIMING2_IEO          BIT23       // Invert Output Enable Signal
#define LCD_LCDTIMING2_IPC          BIT22       // Invert Pixel Clock Signal
#define LCD_LCDTIMING2_IHS          BIT21       // Invert Hsync Signal
#define LCD_LCDTIMING2_IVS          BIT20       // Invert Vsync Signal
#define LCD_LCDTIMING2_ACBI         0x000F0000  // AC Bias Transistion/Interrupt Freq
#define LCD_LCDTIMING2_ACB          0x0000FF00  // Lines/AC Bias Transition Freq
#define LCD_LCDTIMING2_PCD          0x000000FF  // Pixel Clock Divisor
//
// Offset of LCDSUBPANEL register and its register definition.
//
#define LCD_LCDSUBPANEL_SPEN        BIT31       // Sub-Panel Enable.
#define LCD_LCDSUBPANEL_RESV1       BIT30       // Reserved bits.
#define LCD_LCDSUBPANEL_HOLS        BIT29       // High or low threshold.
#define LCD_LCDSUBPANEL_RESV0       0x1c000000  // Reserved bits.
#define LCD_LCDSUBPANEL_LPPT        0x03ff0000  // Line Per Panel Threshold.
#define LCD_LCDSUBPANEL_DPD         0x0000ffff  // Default Pixel Data.
///////////////////////////////////////////////////////////////////////////////
// DMA controller.
///////////////////////////////////////////////////////////////////////////////
#define DMA_BASE                    0xfffed800
#define DMA_LCD_CTRL                (DMA_BASE+0x300)
#define DMA_LCD_TOP_F1_LW           (DMA_BASE+0x302)
#define DMA_LCD_TOP_F1_UW           (DMA_BASE+0x304)
#define DMA_LCD_BOT_F1_LW           (DMA_BASE+0x306)
#define DMA_LCD_BOT_F1_UW           (DMA_BASE+0x308)
#define DMA_LCD_TOP_F2_LW           (DMA_BASE+0x30a)
#define DMA_LCD_TOP_F2_UW           (DMA_BASE+0x30c)
#define DMA_LCD_BOT_F2_LW           (DMA_BASE+0x30e)
#define DMA_LCD_BOT_F2_UW           (DMA_BASE+0x310)
#define DMA_GCR                     (DMA_BASE+0x400)
///////////////////////////////////////////////////////////////////////////////
// McBSP.
///////////////////////////////////////////////////////////////////////////////
#define MCBSP0_BASE                 0xe1011800              // Referred to as Audio McBSP or Com McBSP1
#define MCBSP0_RHEA_CHIP_SELECT     3
#define MCBSP1_BASE                 0xe1017000              // Referred to as Optical McBSP or Com McBSP3
#define MCBSP1_RHEA_CHIP_SELECT     14
#define MCBSP2_BASE                 0xfffb1000              // Referred to as Modem Data I/F (sometimes SPI) McBSP.
#define MCBSP2_RHEA_CHIP_SELECT     2                       // Also referred to as Com McBSP2.