/* *  Copyright 2001 by Texas Instruments Incorporated. *  All rights reserved. Property of Texas Instruments Incorporated. *  Restricted rights to use, duplicate or disclose this code are *  granted through contract. *  U.S. Patent Nos. 5,283,900  5,392,448 *//* "@(#) DSP/BIOS 4.50.2 03-27-01 (barracuda-i02)" *//******************************************************************************\*           Copyright (C) 2000 Texas Instruments Incorporated.*                           All Rights Reserved*------------------------------------------------------------------------------* FILENAME...... csl_legacy.h* DATE CREATED.. 04/24/2000 * LAST MODIFIED. 10/30/2001 -                            EMIF_GBLCTL_NOHOLD_0 => EMIF_GBLCTL_NOHOLD_DISABLE                           EMIF_GBLCTL_NOHOLD_1 => EMIF_GBLCTL_NOHOLD_ENABLE                           MCBSP : Baseaddr => baseaddr\******************************************************************************/#ifndef _CSL_LEGACY_H_#define _CSL_LEGACY_H_#include <csl_legacyhal.h>/******************************************************************************\* scope and inline control macros\******************************************************************************/#ifdef __cplusplus#define CSLAPI extern "C" far#else#define CSLAPI extern far#endif#undef  USEDEFS#undef  IDECL#undef  IDEF#ifdef  _LEGACY_MOD_  #define IDECL CSLAPI  #define USEDEFS  #define IDEF#else  #ifdef  _INLINE    #define IDECL static inline    #define USEDEFS    #define IDEF  static inline  #else    #define IDECL CSLAPI  #endif#endif/******************************************************************************\* global macro declarations\******************************************************************************/#if (CACHE_SUPPORT)  #define CACHE_64KSRAM        CACHE_64KSRAM   #define CACHE_0KCACHE        CACHE_0KCACHE   #define CACHE_48KSRAM        CACHE_48KSRAM   #define CACHE_16KCACHE       CACHE_16KCACHE  #define CACHE_32KSRAM        CACHE_32KSRAM   #define CACHE_32KCACHE       CACHE_32KCACHE  #define CACHE_16KSRAM        CACHE_16KSRAM   #define CACHE_48KCACHE       CACHE_48KCACHE  #define CACHE_0KSRAM         CACHE_0KSRAM    #define CACHE_64KCACHE       CACHE_64KCACHE  #define CACHE_L2MODE         CACHE_L2Mode   #define CACHE_L2ALL          CACHE_L2ALL  #define CACHE_L1PALL         CACHE_L1PALL  #define CACHE_L1DALL         CACHE_L1DALL  #define CACHE_REGION         CACHE_Region  #define CACHE_PCCMAPPED      CACHE_PCC_MAPPED  #define CACHE_PCCENABLE      CACHE_PCC_ENABLE  #define CACHE_PCCFREEZE      CACHE_PCC_FREEZE  #define CACHE_PCCBYPASS      CACHE_PCC_BYPASS   #define CACHE_PCC            CACHE_Pcc   #define CACHE_Reset          CACHE_reset  #define CACHE_SetL2Mode      CACHE_setL2Mode  #define CACHE_GetL2Mode      CACHE_getL2Mode  #define CACHE_SetPccMode     CACHE_setPccMode  #define CACHE_GetL2SramSize  CACHE_getL2SramSize  //#define CACHE_Init           CACHE_init  #define CACHE_Init()  #define CACHE_EnableCaching  CACHE_enableCaching  #define CACHE_Flush(r,a,w)      CACHE_flush(r,(void*)(a),w)  #define CACHE_Clean(r,a,w)      CACHE_clean(r,(void*)(a),w)  #define CACHE_Invalidate(r,a,w) CACHE_invalidate(r,(void*)(a),w)#endif /* CACHE_SUPPORT */#if (1)  //#define CHIP_Init            CHIP_init   #define CHIP_Init()                #define CHIP_GetCpuId        CHIP_getCpuId  #define CHIP_GetRevId        CHIP_getRevId  #define CHIP_GetEndian       CHIP_getEndian  #define CHIP_GetMapMode      CHIP_getMapMode #endif#if (1)  #define CSL_Init             CSL_init        #define CSLINIT_Init         CSLINIT_init        #define CSLLIB_Init          CSLLIB_init#endif#if (DAT_SUPPORT)  #define DAT_Open             DAT_open    #define DAT_Close            DAT_close       #define DAT_Copy             DAT_copy     #define DAT_Fill             DAT_fill      #define DAT_Wait             DAT_wait    #define DAT_Copy2D           DAT_copy2d     //#define DAT_Init             DAT_init   #define DAT_Init()  #define _DAT_Open            _DAT_open    #define _DAT_Close           _DAT_close       #define _DAT_Copy            _DAT_copy     #define _DAT_Fill            _DAT_fill      #define _DAT_Wait            _DAT_wait    #define _DAT_Copy2D          _DAT_copy2d     #define _DAT_Init            _DAT_init #endif /* DAT_SUPPORT */#if (DMA_SUPPORT)  #define DMA_PRIVATE_OBJ      DMA_PrivateObj  #define DMA_HANDLE           DMA_Handle  #define DMA_CONFIG           DMA_Config  #define DMA_GBL              DMA_Gbl  #define DMA_HCHA0            _DMA_hCha0  #define DMA_HCHA1            _DMA_hCha1  #define DMA_HCHA2            _DMA_hCha2  #define DMA_HCHA3            _DMA_hCha3  #define DMA_GBL_PRIVATE      DMA_gblPrivate   #define DMA_Reset            DMA_reset             #define DMA_Open             DMA_open              #define DMA_Close            DMA_close             #define DMA_ConfigA          DMA_config             #define DMA_ConfigB          DMA_configArgs             #define DMA_AllocGlobalReg   DMA_allocGlobalReg             #define DMA_FreeGlobalReg    DMA_freeGlobalReg             //#define DMA_Init             DMA_init             #define DMA_Init()  #define DMA_GetEventId       DMA_getEventId             #define DMA_GetStatus        DMA_getStatus             #define DMA_Start            DMA_start             #define DMA_Stop             DMA_stop             #define DMA_Pause            DMA_pause             #define DMA_AutoStart        DMA_autoStart             #define DMA_Wait             DMA_wait             #define DMA_SetAuxCtl        DMA_setAuxCtl             #define DMA_GetGlobalReg     DMA_getGlobalReg             #define DMA_SetGlobalReg     DMA_setGlobalReg           #if (0)  #define DMA_GBL_ADDRRLDB    0x00000001u  #define DMA_GBL_ADDRRLDC    0x00000002u  #define DMA_GBL_ADDRRLDD    0x00000003u  #define DMA_GBL_INDEXA      0x00000004u  #define DMA_GBL_INDEXB      0x00000005u  #define DMA_GBL_CNTRLDA     0x00000008u  #define DMA_GBL_CNTRLDB     0x00000009u  #define DMA_GBL_SPLITA      0x0000000Du  #define DMA_GBL_SPLITB      0x0000000Eu  #define DMA_GBL_SPLITC      0x0000000Fu  #define _DMA_GBLREG_CNT     16  #define _DMA_GBLREG_MASK    (_DMA_GBLREG_CNT-1)#endif  #define DMA_MK_AUXCTL(chpri,auxpri) ((Uint32)(\      HFIELD_SHIFT(HDMA_AUXCTL_CHPRI,chpri)|\      HFIELD_SHIFT(HDMA_AUXCTL_AUXPRI,auxpri)\    )\  )  #define DMA_MK_PRICTL(start,srcdir,dstdir,esize,split,cntrld,\    index,rsync,wsync,pri,tcint,fs,emod,srcrld,dstrld) ((UINT32)(\      HFIELD_SHIFT(HDMA_PRICTL_START,start)|\      HFIELD_SHIFT(HDMA_PRICTL_SRCDIR,srcdir)|\      HFIELD_SHIFT(HDMA_PRICTL_DSTDIR,dstdir)|\      HFIELD_SHIFT(HDMA_PRICTL_ESIZE,esize)|\      HFIELD_SHIFT(HDMA_PRICTL_SPLIT,split)|\      HFIELD_SHIFT(HDMA_PRICTL_CNTRLD,cntrld)|\      HFIELD_SHIFT(HDMA_PRICTL_INDEX,index)|\      HFIELD_SHIFT(HDMA_PRICTL_RSYNC,rsync)|\      HFIELD_SHIFT(HDMA_PRICTL_WSYNC,wsync)|\      HFIELD_SHIFT(HDMA_PRICTL_PRI,pri)|\      HFIELD_SHIFT(HDMA_PRICTL_TCINT,tcint)|\      HFIELD_SHIFT(HDMA_PRICTL_FS,fs)|\      HFIELD_SHIFT(HDMA_PRICTL_EMOD,emod)|\      HFIELD_SHIFT(HDMA_PRICTL_SRCRLD,srcrld)|\      HFIELD_SHIFT(HDMA_PRICTL_DSTRLD,dstrld)\    )\  )  #define DMA_MK_SECCTL(sxie,frameie,lastie,blockie,rdropie,wdropie,\    dmacen,fsig,rspol,wspol) ((UINT32)(\      HFIELD_SHIFT(HDMA_SECCTL_SXIE,sxie)|\      HFIELD_SHIFT(HDMA_SECCTL_FRAMEIE,frameie)|\      HFIELD_SHIFT(HDMA_SECCTL_LASTIE,lastie)|\      HFIELD_SHIFT(HDMA_SECCTL_BLOCKIE,blockie)|\      HFIELD_SHIFT(HDMA_SECCTL_RDROPIE,rdropie)|\      HFIELD_SHIFT(HDMA_SECCTL_WDROPIE,wdropie)|\      HFIELD_SHIFT(HDMA_SECCTL_DMACEN,dmacen)|\      HFIELD_SHIFT(HDMA_SECCTL_FSIG,fsig)|\      HFIELD_SHIFT(HDMA_SECCTL_RSPOL,rspol)|\      HFIELD_SHIFT(HDMA_SECCTL_WSPOL,wspol)\    )\  )  #define DMA_MK_SRC(src) ((Uint32)(\      HFIELD_SHIFT(HDMA_SRC_SRC,src)\    )\  )  #define DMA_MK_DST(dst) ((Uint32)(\      HFIELD_SHIFT(HDMA_DST_DST,dst)\    )\  )  #define DMA_MK_XFRCNT(elecnt,frmcnt) ((Uint32)(\      HFIELD_SHIFT(HDMA_XFRCNT_ELECNT,elecnt)|\      HFIELD_SHIFT(HDMA_XFRCNT_FRMCNT,frmcnt)\    )\  )  #define DMA_MK_GBLCNT(elecnt,frmcnt) ((Uint32)(\      HFIELD_SHIFT(HDMA_GBLCNT_ELECNT,elecnt)|\      HFIELD_SHIFT(HDMA_GBLCNT_FRMCNT,frmcnt)\    )\  )  #define DMA_MK_GBLIDX(eleidx,frmidx) ((Uint32)(\      HFIELD_SHIFT(HDMA_GBLIDX_ELEIDX,eleidx)|\      HFIELD_SHIFT(HDMA_GBLIDX_FRMIDX,frmidx)\    )\  )  #define DMA_MK_GBLADDR(gbladdr) ((Uint32)(\      HFIELD_SHIFT(HDMA_GBLADDR_GBLADDR,gbladdr)\    )\  )#endif /* DMA_SUPPORT */#if (EDMA_SUPPORT)  #define EDMA_HANDLE          EDMA_Handle  #define EDMA_CONFIG          EDMA_Config  #define EDMA_Reset           EDMA_reset  #define EDMA_Open            EDMA_open  #define EDMA_Close           EDMA_close  #define EDMA_AllocTable      EDMA_allocTable  #define EDMA_FreeTable       EDMA_freeTable  #define EDMA_ConfigA         EDMA_config  #define EDMA_ConfigB         EDMA_configArgs  //#define EDMA_Init            EDMA_init                #define EDMA_Init()   #define EDMA_GetScratchAddr  EDMA_getScratchAddr                #define EDMA_GetScratchSize  EDMA_getScratchSize                #define EDMA_GetPriQStatus   EDMA_getPriQStatus                #define EDMA_EnableChannel   EDMA_enableChannel      #define EDMA_DisableChannel  EDMA_disableChannel                #define EDMA_SetChannel      EDMA_setChannel                #define EDMA_GetChannel      EDMA_getChannel                #define EDMA_ClearChannel    EDMA_clearChannel                #define EDMA_GetTableAddress EDMA_getTableAddress                #if (0)    #define EDMA_CCER            HEDMA_CCER    #define EDMA_CIPR            HEDMA_CIPR    #define EDMA_CIER            HEDMA_CIER  #endif  #define EDMA_MK_OPT(fs,link,tcc,tcint,dum,d2d,sum,s2d,esize,pri)\    ((Uint32)( \      HFIELD_SHIFT(HEDMA_OPT_FS,fs)| \      HFIELD_SHIFT(HEDMA_OPT_LINK,link)| \      HFIELD_SHIFT(HEDMA_OPT_TCC,tcc)| \      HFIELD_SHIFT(HEDMA_OPT_TCINT,tcint)| \