?? switest.cdb.fri_mar_23_11.41.23_2007
字號:
}
global DISPCALLCSLCFGINIT :: = (self.CHIPTYPE != "other" && self.CHIPTYPE != "custom") {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "Call CSL_cfgInit Initialization routine"
prop Visible :: 0
prop Writable :: self.SUPPORTCSL
prop NoGen :: 1
}
global DSPNAME :: "c28xx" {
prop Type :: "{21455EA3-B96A-11cf-9BFE-0000C0AC14C7}"
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global MODIFYPLLCR :: 1 {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "Initialize PLLCR"
prop JSName :: "MODIFYPLLCR"
prop Visible :: 1
prop Writable :: 1
prop NoGen :: 0
prop Set :: (if ($1 != self.MODIFYPLLCR) {self.MODIFYPLLCR = $1} , "ok")
}
global PLLCR :: 10 {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Format :: "0x%01x"
prop Style :: 0x01 | 0x02
prop Label :: "PLLCR Register value"
prop JSName :: "PLLCR"
prop Visible :: 1
prop Writable :: self.MODIFYPLLCR
prop NoGen :: 0
}
global PLLWAITCYCLE :: 131072 {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Format :: "%d"
prop Style :: 0x20
prop Label :: "Cycles to wait for PLL lock"
prop JSName :: "PLLWAITCYCLE"
prop Visible :: 1
prop Writable :: self.MODIFYPLLCR
prop NoGen :: 0
}
global DSPARITHMETIC :: = (if (GBL.DSPTYPE == 62 && (GBL.DSPSUBTYPE / 100) == 67) {"FLOAT"} else {"FIXED"}) {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "FIXED,FLOAT"
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global DSPWORDSIZE :: = (if (GBL.DSPTYPE == 30 || GBL.DSPTYPE == 40 || GBL.DSPTYPE == 62) {32} else {16}) {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "DSP Word Size"
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global DSPCHARSIZE :: = (if GBL.DSPTYPE == 62 {8} else {GBL.DSPWORDSIZE}) {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "DSP Byte Size"
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global DATAPTRSIZE :: = (if (GBL.DSPTYPE == 62) {32} else {if (GBL.DSPTYPE == 54) {16} else {if (GBL.DSPTYPE == 55) {if (GBL.MEMORYMODEL == "SMALL") {16} else {23}} else {if (GBL.DSPTYPE == 28) {22} else {0}}}}) {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop iComment :: "Size of the Data Pointer"
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global CODEPTRSIZE :: = (if (GBL.DSPTYPE == 62) {32} else {if (GBL.DSPTYPE == 54) {if (GBL.CALLMODEL == "near") {16} else {24}} else {if (GBL.DSPTYPE == 55) {24} else {if (GBL.DSPTYPE == 28) {22} else {0}}}}) {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop iComment :: "Size of Code Pointer"
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global MEMORYMODEL :: "LARGE" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "LARGE"
prop Label :: "Memory Model"
prop JSName :: "MEMORYMODEL"
prop Visible :: 1
prop Writable :: 1
prop NoGen :: 1
}
global AUTOINIT :: "ROM" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "ROM,RAM"
prop Label :: "C Autoinitialization Model"
prop Visible :: 0
prop Writable :: 1
prop NoGen :: 1
}
global USERINIT :: 0 {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "Call User Init Function"
prop JSName :: "CALLUSERINITFXN"
prop Visible :: 1
prop Writable :: 1
prop NoGen :: 0
prop Set :: (if ($1 == 0) {self.USERINITFXN = @_FXN_F_nop, self.USERINIT = $1} else {self.USERINIT = $1}, "ok")
}
global USERINITFXN :: @_FXN_F_nop {
prop Type :: "{7C434D00-1629-11d0-9BFE-0000C0AC14C7}"
prop Label :: "User Init Function"
prop JSName :: "USERINITFXN"
prop Visible :: 1
prop Writable :: self.USERINIT
prop NoGen :: 0
}
global OLDAUTOCALCULATE :: 1 {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "previous value for autocalculate"
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global ENABLEINST :: 1 {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "Enable Real Time Analysis"
prop JSName :: "ENABLEINST"
prop Visible :: 1
prop Writable :: 1
prop NoGen :: 0
prop Set :: (if ($1 != self.ENABLEINST) {if ($1) {RTA_toHost.Create("HST"), RTA_fromHost.Create("HST"), RTA_dispatcher.Create("HST"), IDL_busyObj.Create("IDL"), IDL.USEIDLBUSYOBJ = 1, IDL_cpuLoad.Create("IDL"), IDL.AUTOCALCULATE = self.OLDAUTOCALCULATE} else {RTA_toHost.Delete("HST"), RTA_fromHost.Delete("HST"), RTA_dispatcher.Delete("HST"), IDL_busyObj.Delete("IDL"), IDL.USEIDLBUSYOBJ = 0, IDL_cpuLoad.Delete("IDL"), self.OLDAUTOCALCULATE = IDL.AUTOCALCULATE, IDL.AUTOCALCULATE = 0}, self.ENABLEINST = $1} , "ok")
}
global CGENERATE :: 1 {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "Do C Generation"
prop Visible :: 0
prop Writable :: 1
prop NoGen :: 1
}
global LARGEMODEL :: = if self.MEMORYMODEL == "LARGE" {1} else {0} {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 0
}
global SUPPORTCSL :: = self.CHIPTYPE != "other" {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop NoGen :: 0
}
global ENABLEALLTRC :: 1 {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "Enable All TRC Trace Event Classes"
prop JSName :: "ENABLEALLTRC"
prop Visible :: 1
prop Writable :: 1
prop NoGen :: 1
prop Set :: (if ($1) {self.TRCMASKVALUE = 0xDBEF} else {self.TRCMASKVALUE = 0x4000}, self.ENABLEALLTRC = $1, "ok")
}
global TRCMASKVALUE :: 56303 {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop NoGen :: 0
}
global CALLCSLCFGINIT :: = self.DISPCALLCSLCFGINIT {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop NoGen :: 0
}
global CDBPATH :: "" {
prop Type :: "{21455EA3-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "CDB search path in COFF file"
prop JSName :: "CDBRELATIVEPATH"
prop Visible :: 1
prop Writable :: 1
prop NoGen :: 1
}
}
type MEM {
isa ObjectMgr
prop Label :: "MEM - Memory Section Manager"
prop name :: "MEM"
prop DependsOn :: "SEM"
prop IsContainedIn :: SYSTEM
prop GlobalIcon :: 115
prop InstanceIcon :: 116
prop GlobalHelpTopic :: (108)
prop InstanceHelpTopic :: (208)
prop InstancePropertyPage :: ("{3D658E70-05E7-11d0-BD44-0020AFEE33C8}")
prop GlobalPropertyPage :: ("{3D658E71-05E7-11d0-BD44-0020AFEE33C8}")
prop GenLinkPrologue :: (if (GBL.DSPTYPE == 55) {"-stack 0x%1x\n-sysstack 0x%2x\n\nSECTIONS { .sysstack : block(0x20000) fill = 0xfeeb {%12t\nGBL_sysstackbeg = .;\n*(.sysstack)\nGBL_sysstackend = GBL_sysstackbeg + 0x%2x -1 ;%12t\n _HWI_SYSSTKTOP = GBL_sysstackbeg; %12t\n _HWI_SYSSTKBOTTOM =
(GBL_sysstackend+1);\n%8t} > %3s}%0t\n\nMEMORY {%4t\0, _cmd55stksz, _cmd55systksz, _sysstackSeg"} else {"-stack 0x%1x\nMEMORY {%4t\0, _stackSize"})
prop _stackSize :: MEM.STACKSIZE
prop AllocType :: (if (self.REUSE == 0 && self.USERCMD == 0) {"21\0, _argsString, _argsSeg, _midPlace, \
_sysdataString, _sysdataSeg, _thirdPlace, \
_trcinitString, _trcinitSeg, _midPlace, \
_gblinitString, _gblinitSeg, _midPlace, \
_memObjString, _memObjSeg, _midPlace, \
_sysinitString, _initSeg, _sysinitPlace, \
_sysregsString, _regsSeg, _midPlace, \
_bssString, _bssSeg, _firstPlace, \
_ebssString, _ebssSeg, _midPlace, \
_econstString, _econstSeg, _midPlace, \
_farString, _farSeg, _secondPlace, \
_cinitString, _cinitSeg, _midPlace, \
_pinitString, _pinitSeg, _midPlace, \
_dataString, _dataSeg, _midPlace, \
_constString, _constSeg, _midPlace, \
_switchString, _switchSeg, _midPlace, \
_cioString, _cioSeg, _midPlace, \
_textString, _textSeg, _midPlace, \
_frtString, _frtSeg, _midPlace, \
_biosString, _biosSeg, _midPlace, \
_stackString, _stackSeg, _midPlace"} else {if (self.REUSE == 0 && self.USERCMD == 1) {"9\0, _argsString, _argsSeg, _midPlace, \
_sysdataString, _sysdataSeg, _thirdPlace, \
_trcinitString, _trcinitSeg, _midPlace, \
_gblinitString, _gblinitSeg, _midPlace, \
_memObjString, _memObjSeg, _midPlace, \
_sysinitString, _initSeg, _sysinitPlace, \
_sysregsString, _regsSeg, _midPlace, \
_biosString, _biosSeg, _midPlace, \
_stackString, _stackSeg, _midPlace"} else {if (self.REUSE == 1 && self.USERCMD == 0) {"20\0, _argsString, _argsSeg, _midPlace, \
_sysdataString, _sysdataSeg, _thirdPlace, \
_trcinitString, _trcinitSeg, _midPlace, \
_gblinitString, _gblinitSeg, _midPlace, \
_memObjString, _memObjSeg, _midPlace, \
_sysregsString, _regsSeg, _midPlace, \
_bssString, _bssSeg, _firstPlace, \
_ebssString, _ebssSeg, _midPlace, \
_econstString, _econstSeg, _midPlace, \
_farString, _farSeg, _secondPlace, \
_cinitString, _cinitSeg, _midPlace, \
_pinitString, _pinitSeg, _midPlace, \
_dataString, _dataSeg, _midPlace, \
_constString, _constSeg, _midPlace, \
_switchString, _switchSeg, _midPlace, \
_cioString, _cioSeg, _midPlace, \
_textString, _textSeg, _midPlace, \
_frtString, _frtSeg, _midPlace, \
_biosString, _biosSeg, _midPlace, \
_stackString, _stackSeg, _midPlace"} else {"8\0, _argsString, _argsSeg, _midPlace, \
_sysdataString, _sysdataSeg, _thirdPlace, \
_trcinitString, _trcinitSeg, _midPlace, \
_gblinitString, _gblinitSeg, _midPlace, \
_memObjString, _memObjSeg, _midPlace, \
_sysregsString, _regsSeg, _midPlace, \
_biosString, _biosSeg, _midPlace, \
_stackString, _stackSeg, _midPlace"}}})
prop _firstPlace :: 0
prop _secondPlace :: 0 + 1
prop _thirdPlace :: 0 + 2
prop _midPlace :: (0x7fffff / 2)
prop _sysinitPlace :: (0x7fffff / 2)
prop _argsString :: ("%8t .args: fill=0 {%12t\n *(.args)\n . += 0x%1x;%8t\n }\0, _argsSize")
prop _bssString :: ("%8t .bss: {}")
prop _ebssString :: ("%8t .ebss: {}")
prop _econstString :: (if (self.ENABLELOADSEG == 1) {if (MEM.ECONSTSEG == MEM.LOADECONSTSEG) {"%8t .econst: {}"} else {if (MEM.LOADECONSTSEG.space() == "data") {"%8t .econst: {} load > %1s PAGE 1, run\0, _loadeconstSeg, _pg"} else {"%8t .econst: {} load > %1s PAGE 0, run\0, _loadeconstSeg, _pg"}}} else {"%8t .econst: {}"})
prop _farString :: ("%8t .far: {}")
prop _cinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.CINITSEG == MEM.LOADCINITSEG) {"%8t .cinit: {}"} else {"%8t .cinit: {} load > %1s%2s, run\0, _loadcinitSeg, _cinitpg"}} else {"%8t .cinit: {}"})
prop _pinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.PINITSEG == MEM.LOADPINITSEG) {"%8t .pinit: {}"} else {"%8t .pinit: {} load > %1s%2s, run\0, _loadpinitSeg, _pinitpg"}} else {"%8t .pinit: {}"})
prop _trcinitString :: (if (self.ENABLELOADSEG == 1) {"%8t .trcdata: START(_trcdata_loadstart), END(_trcdata_loadend), SIZE(_trcdata_loadsize), RUN_START(_trcdata_runstart) {\n %8t} load > %1s%2s, run\0, _loadtrcinitSeg, _trcdatapg"} else {"%8t .trcdata: START(_trcdata_loadstart), END(_trcdata_loadend), SIZE(_trcdata_loadsize), RUN_START(_trcdata_runstart) {\n %8t}"})
prop _gblinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.BIOSINITSEG == MEM.LOADBIOSINITSEG) {"%8t .gblinit: {}"} else {"%8t .gblinit: {} load > %1s%2s, run\0, _loadgblinitSeg, _gblinitpg"}} else {"%8t .gblinit: {}"})
prop _dataString :: (if (self.ENABLELOADSEG == 1) {if (MEM.DATASEG == MEM.LOADDATASEG) {"%8t .data: {}"} else {if (MEM.LOADDATASEG.space() == "data") {"%8t .data: {} load > %1s PAGE 1, run\0, _loaddataSeg"} else {"%8t .data: {} load > %1s PAGE 0, run\0, _loaddataSeg"}}} else {"%8t .data: {}"})
prop _constString :: (if (self.ENABLELOADSEG == 1) {if (MEM.CONSTSEG == MEM.LOADCONSTSEG) {"%8t .const: {}"} else {if ((28 == 54) || (28 == 28)) {"%8t .const: {} load > %1s PAGE %2s, run\0, _loadconstSeg, _pg"} else {"%8t .const: {} load > %1s, run\0, _loadconstSeg"}}} else {"%8t .const: {}"})
prop _switchString :: (if (self.ENABLELOADSEG == 1) {if (MEM.SWITCHSEG == MEM.LOADSWITCHSEG) {"%8t .switch: {}"} else {"%8t .switch: {} load > %1s%2s, run\0, _loadswitchSeg, _switchpg"}} else {"%8t .switch: {}"})
prop _sysmemString :: ("%8t .sysmem: {}")
prop _cioString :: ("%8t .cio: {}")
prop _memObjString :: ("%8t .mem: {}")
prop _sysdataString :: (if ((GBL.ROM == 0) && (GBL.DSPTYPE == 54)) {"%8t .sysdata: align = 128 {%12t\n GBL_A_SYSPAGE = .;\n GBL_A_SYSDP = GBL_A_SYSPAGE >> 7;\n %8t }"} else {"%8t .sysdata: {}"})
prop _sysinitString :: (if (self.ENABLELOADSEG == 1) {if (MEM.INITSEG == MEM.LOADINITSEG) {"%8t .sysinit: {}"} else {"%8t .sysinit: {} load > %1s%2s, run\0, _loadinitSeg, _sysinitpg"}} else {"%8t .sysinit: {}"})
prop _sysregsString :: ("%8t .sysregs: {}")
prop _textString :: (if (self.ENABLELOADSEG == 1) {if (MEM.TEXTSEG == MEM.LOADTEXTSEG) {"%8t .text: {}"} else {"%8t .text: {} load > %1s%2s, run\0, _loadtextSeg, _textpg"}} else {"%8t .text: {}"})
prop _frtString :: ("%8t frt: {}")
prop _biosString :: (if (self.ENABLELOADSEG == 1) {if (MEM.BIOSSEG == MEM.LOADBIOSSEG) {"%8t .bios: {}"} else {"%8t .bios: {} load > %1s%2s, run\0, _loadbiosSeg, _biospg"}} else {"%8t .bios: {}"})
prop _stackString :: (if (GBL.DSPTYPE == 62) {"%8t .stack: fill=0xc0ffee {%12t\n GBL_stackbeg = .;\n *(.stack)\n GBL_stackend = GBL_stackbeg + 0x%1x - 1;%12t\n _HWI_STKBOTTOM = GBL_stackbeg + 0x%1x - 4 & ~7;%12t\n _HWI_STKTOP = GBL_stackbeg;%8t\n }\0, _stackSize, _stackSize"} else {if (GBL.DSPTYPE == 54) {"%8t .stack: fill=0xbeef {%12t\n GBL_stackbeg = .;\n *(.stack)\n GBL_stackend = ((GBL_stackbeg + 0x%1x - 1) & 0xfffe) ;%8t\n _HWI_STKBOTTOM = GBL_stackend;%12t\n _HWI_STKTOP = GBL_stackbeg;%8t\n }\0, _stackSize"} else {if (GBL.DSPTYPE == 55) {"%8t .stack: block(0x20000) fill=0xbeef {%12t\n GBL_stackbeg = .;\n *(.stack)\n GBL_stackend = (GBL_stackbeg + 0x%1x - 1) ;%12t\n _HWI_STKBOTTOM = (GBL_stackend+1);%12t\n _HWI_STKTOP = (GBL_stackbeg);%8t\n }\0, _cmd55stksz"} else {"%8t .stack: fill=0xbeef {%12t\n GBL_stackbeg = .;\n *(.stack)\n GBL_stackend = GBL_stackbeg + 0x%1x - 1;%8t\n _HWI_STKBOTTOM = GBL_stackbeg;%12t\n _HWI_STKTOP = (GBL_stackend + 1);%8t\n }\0, _stackSize"}}})
prop _memHdrSize :: 8
prop GenLinkEpilogue :: ("%0t}")
prop _stackSeg :: MEM.STACKSEG
prop _textSeg :: MEM.TEXTSEG
prop _frtSeg :: MEM.TEXTSEG
prop _biosSeg :: MEM.BIOSSEG
prop _dataSeg :: MEM.DATASEG
prop _cioSeg :: MEM.CIOSEG
prop _sysmemSeg :: MEM.SYSMEMSEG
prop _constSeg :: MEM.CONSTSEG
prop _initSeg :: MEM.INITSEG
prop _pinitSeg :: MEM.PINITSEG
prop _trcinitSeg :: MEM.TRCINITSEG
prop _gblinitSeg :: MEM.BIOSINITSEG
prop _regsSeg :: MEM.SYSDATASEG
prop _sysdataSeg :: MEM.SYSDATASEG
prop _argsSeg :: MEM.ARGSSEG
prop _argsSize :: MEM.ARGSSIZE
prop _bssSeg :: MEM.BSSSEG
prop _ebssSeg :: MEM.EBSSSEG
prop _econstSeg :: MEM.ECONSTSEG
prop _farSeg :: MEM.FARSEG
prop _cinitSeg :: MEM.CINITSEG
prop _memObjSeg :: MEM.CFGOBJSEG
prop _switchSeg :: MEM.SWITCHSEG
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