?? yimaqi.rpt
字號:
ispEXPERT Compiler Release 8.1.19.32, Jun 28 2000 11:25:29
Design Parameters
-----------------
EFFORT: MEDIUM (2)
IGNORE_FIXED_PIN: OFF
MAX_GLB_IN: 16
MAX_GLB_OUT: 4
OS_VERSION: Windows NT 5.0
PARAM_FILE: _yimaqi
PIN_FILE: yimaqi.xpn
STRATEGY: DELAY
TIMING_ANALYZER: FREQUENCY SETUP_HOLD CLOCK_TO_OUTPUT PRIMARY_IN_TO_OUT
USE_GLOBAL_RESET: ON
XOR: OFF
Design Specification
--------------------
Design: yimaqi
Part: ispLSI1032E-100LJ84
ISP: ON
PULL: UP
SECURITY: OFF
SLOWSLEW: OFF
Number of Critical Pins: 0
Number of Free Pins: 11
Number of Locked Pins: 0
Number of Reserved Pins: 0
Input Pins
Pin Name Pin Attribute
A PULLUP
B PULLUP
C PULLUP
Output Pins
Pin Name Pin Attribute
Y0 PULLUP
Y1 PULLUP
Y2 PULLUP
Y3 PULLUP
Y4 PULLUP
Y5 PULLUP
Y6 PULLUP
Y7 PULLUP
Pre-Route Design Statistics
---------------------------
Number of Macrocells: 8
Number of GLBs: 2
Number of I/Os: 11
Number of Nets: 11
Number of Free Inputs: 3
Number of Free Outputs: 8
Number of Free Three-States: 0
Number of Free Bidi's: 0
Number of Locked Input IOCs: 0
Number of Locked DIs: 0
Number of Locked Outputs: 0
Number of Locked Three-States: 0
Number of Locked Bidi's: 0
Number of CRIT Outputs: 0
Number of Global OEs: 0
Number of External Clocks: 0
GLB Utilization (Out of 32): 6%
I/O Utilization (Out of 68): 16%
Net Utilization (Out of 196): 5%
Nets with Fanout of 1: 8
Nets with Fanout of 2: 3
Average Fanout per Net: 1.27
GLBs with 3 Input(s): 2
Average Inputs per GLB: 3.00
GLBs with 4 Output(s): 2
Average Outputs per GLB: 4.00
Number of GLB Registers: 0
Number of IOC Registers: 0
Post-Route Design Implementation
--------------------------------
Number of Macrocells: 8
Number of GLBs: 2
Number of IOCs: 11
Number of DIs: 0
Number of GLB Levels: 1
GLB glb00, D6
3 Input(s)
(A.O, AX, I15), (B.O, BX, I4), (C.O, CX, I14)
4 Output(s)
(AND_735, O0), (AND_730, O1), (AND_729, O2), (AND_728, O3)
4 Product Term(s)
Output AND_735
3 Input(s)
BX, AX, CX
1 Fanout(s)
Y7.IR
1 Product Term(s)
1 GLB Level(s)
AND_735 = !CX & !BX & !AX
Output AND_730
3 Input(s)
BX, AX, CX
1 Fanout(s)
Y2.IR
1 Product Term(s)
1 GLB Level(s)
AND_730 = AX & CX & !BX
Output AND_729
3 Input(s)
BX, AX, CX
1 Fanout(s)
Y1.IR
1 Product Term(s)
1 GLB Level(s)
AND_729 = AX & BX & !CX
Output AND_728
3 Input(s)
BX, AX, CX
1 Fanout(s)
Y0.IR
1 Product Term(s)
1 GLB Level(s)
AND_728 = AX & BX & CX
GLB glb01, A6
3 Input(s)
(A.O, AX, I0), (B.O, BX, I11), (C.O, CX, I1)
4 Output(s)
(AND_734, O0), (AND_733, O1), (AND_732, O2), (AND_731, O3)
4 Product Term(s)
Output AND_734
3 Input(s)
BX, AX, CX
1 Fanout(s)
Y6.IR
1 Product Term(s)
1 GLB Level(s)
AND_734 = CX & !BX & !AX
Output AND_733
3 Input(s)
BX, AX, CX
1 Fanout(s)
Y5.IR
1 Product Term(s)
1 GLB Level(s)
AND_733 = BX & !CX & !AX
Output AND_732
3 Input(s)
BX, AX, CX
1 Fanout(s)
Y4.IR
1 Product Term(s)
1 GLB Level(s)
AND_732 = BX & CX & !AX
Output AND_731
3 Input(s)
BX, AX, CX
1 Fanout(s)
Y3.IR
1 Product Term(s)
1 GLB Level(s)
AND_731 = AX & !CX & !BX
Input A, IO11
Output AX
2 Fanout(s)
glb01.I0, glb00.I15
Input B, IO43
Output BX
2 Fanout(s)
glb01.I11, glb00.I4
Input C, IO1
Output CX
2 Fanout(s)
glb01.I1, glb00.I14
Output Y0, IO51
Input (glb00.O3, AND_728)
Y0 = !AND_728
Output Y1, IO50
Input (glb00.O2, AND_729)
Y1 = !AND_729
Output Y2, IO49
Input (glb00.O1, AND_730)
Y2 = !AND_730
Output Y3, IO3
Input (glb01.O3, AND_731)
Y3 = !AND_731
Output Y4, IO2
Input (glb01.O2, AND_732)
Y4 = !AND_732
Output Y5, IO5
Input (glb01.O1, AND_733)
Y5 = !AND_733
Output Y6, IO0
Input (glb01.O0, AND_734)
Y6 = !AND_734
Output Y7, IO48
Input (glb00.O0, AND_735)
Y7 = !AND_735
GLB and GLB Output Statistics
GLB Name, Location GLB Statistics GLB Output Statistics
GLB Output Name Ins, Outs, PTs Ins, FOs, PTs, Levels, PTSABP
glb00, D6 3, 4, 4
AND_728 3, 1, 1, 1, 1PT
AND_729 3, 1, 1, 1, 1PT
AND_730 3, 1, 1, 1, 1PT
AND_735 3, 1, 1, 1, 1PT
glb01, A6 3, 4, 4
AND_731 3, 1, 1, 1, 1PT
AND_732 3, 1, 1, 1, 1PT
AND_733 3, 1, 1, 1, 1PT
AND_734 3, 1, 1, 1, 1PT
Pin Assignments
Pin Name Pin Assignment Pin Type, Pin Attribute
Y7 3 Output, PULLUP
Y2 4 Output, PULLUP
Y1 5 Output, PULLUP
Y0 6 Output, PULLUP
Y6 26 Output, PULLUP
C 27 Input, PULLUP
Y4 28 Output, PULLUP
Y3 29 Output, PULLUP
Y5 31 Output, PULLUP
A 37 Input, PULLUP
B 79 Input, PULLUP
Design process management completed successfully
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